DSPIC30F2010 datasheet(86/202 Pages) MICROCHIP

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dsPIC30F2010

DS70118J-page 86

14.5.1

DUTY CYCLE REGISTER BUFFERS

The four PWM duty cycle registers are double-buffered

to allow glitchless updates of the PWM outputs. For

each duty cycle, there is a duty cycle register that is

accessible by the user and a second duty cycle register

that holds the actual compare value used in the present

PWM period.

For edge-aligned PWM output, a new duty cycle value

will be updated whenever a match with the PTPER reg-

ister occurs and PTMR is reset. The contents of the

duty cycle buffers are automatically loaded into the

duty cycle registers when the PWM time base is dis-

abled (PTEN = 0) and the UDIS bit is cleared in

PWMCON2.

When the PWM time base is in the Up/Down Counting

mode, new duty cycle values are updated when the

value of the PTMR register is zero and the PWM time

base begins to count upwards. The contents of the duty

cycle buffers are automatically loaded into the duty

cycle registers when the PWM time base is disabled

(PTEN = 0).

When the PWM time base is in the Up/Down Counting

mode with double updates, new duty cycle values are

updated when the value of the PTMR register is zero,

and when the value of the PTMR register matches the

value in the PTPER register. The contents of the duty

cycle buffers are automatically loaded into the duty

cycle registers when the PWM time base is disabled

(PTEN = 0).

14.6

Complementary PWM Operation

In the Complementary mode of operation, each pair of

PWM outputs is obtained by a complementary PWM

signal. A dead time may be optionally inserted during

device switching, when both outputs are inactive for a

short period (Refer to Section 14.7 “Dead-Time

Generators”).

In Complementary mode, the duty cycle comparison

units are assigned to the PWM outputs as follows:

• PDC1 register controls PWM1H/PWM1L outputs

• PDC2 register controls PWM2H/PWM2L outputs

• PDC3 register controls PWM3H/PWM3L outputs

The Complementary mode is selected for each PWM

I/O pin pair by clearing the appropriate PMODx bit in the

PWMCON1 SFR. The PWM I/O pins are set to

Complementary mode by default upon a device Reset.

14.7

Dead-Time Generators

Dead-time generation may be provided when any of

the PWM I/O pin pairs are operating in the Comple-

mentary Output mode. The PWM outputs use Push-

Pull drive circuits. Due to the inability of the power out-

put devices to switch instantaneously, some amount of

time must be provided between the turn off event of one

PWM output in a complementary pair and the turn on

event of the other transistor.

14.7.1

DEAD-TIME GENERATORS

Each complementary output pair for the PWM module

has a 6-bit down counter that is used to produce the

dead-time insertion. As shown in Figure 14-4, the

dead-time unit has a rising and falling edge detector

connected to the duty cycle comparison output.

14.7.2

DEAD-TIME RANGES

The amount of dead time provided by the dead-time

unit is selected by specifying the input clock prescaler

value and a 6-bit unsigned value.

Four input clock prescaler selections have been pro-

vided to allow a suitable range of dead times, based on

the device operating frequency. The dead-time clock

prescaler value is selected using the DTAPS<1:0> and

DTBPS<1:0> control bits in the DTCON1 SFR. One of

four clock prescaler options (TCY, 2 TCY, 4 TCY or 8 TCY)

is selected for the dead-time value.

After the prescaler value is selected, the dead time is

adjusted by loading a 6-bit unsigned value into the

DTCON1 SFR.

The dead-time unit prescaler is cleared on the following

events:

• On a load of the down timer due to a duty cycle

comparison edge event.

• On a write to the DTCON1 register.

• On any device Reset.

Note:

The user should not modify the DTCON1

values while the PWM module is operat-

ing (PTEN = 1). Unexpected results may

occur.

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