DSPIC30F2010 datasheet(118/202 Pages) MICROCHIP

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dsPIC30F2010

DS70118J-page 118

18.9

Module Power-Down Modes

The module has three internal power modes. When the

ADON bit is ‘1’, the module is in Active mode; it is fully

powered and functional. When ADON is ‘0’, the module

is in Off mode. The digital and analog portions of the

circuit are disabled for maximum current savings. In

order to return to the Active mode from Off mode, the

user must wait for the ADC circuitry to stabilize.

18.10 A/D Operation During CPU Sleep

and Idle Modes

18.10.1

A/D OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’.

If Sleep occurs in the middle of a conversion, the con-

version is aborted. The converter will not continue with

a partially completed conversion on exit from Sleep

mode.

entering or leaving Sleep mode.

The A/D module can operate during Sleep mode if the

A/D clock source is set to RC (ADRC = 1). When the

RC clock source is selected, the A/D module waits one

instruction cycle before starting the conversion. This

allows the SLEEP instruction to be executed, which

eliminates all digital switching noise from the conver-

sion. When the conversion is complete, the DONE bit

will be set and the result loaded into the ADCBUF

If the A/D interrupt is enabled, the device will wake-up

from Sleep. If the A/D interrupt is not enabled, the A/D

module will then be turned off, although the ADON bit

will remain set.

18.10.2

A/D OPERATION DURING CPU IDLE

MODE

The ADSIDL bit selects if the module will stop on Idle or

continue on Idle. If ADSIDL = 0, the module will con-

tinue

operation

assertion

Idle

mode.

ADSIDL = 1, the module will stop on Idle.

18.11 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off, and any

conversion and acquisition sequence is aborted. The

values that are in the ADCBUF registers are not modi-

fied. The A/D result register will contain unknown data

after a Power-on Reset.

18.12 Output Formats

The A/D result is 10 bits wide. The data buffer RAM is

also 10 bits wide. The 10-bit data can be read in one of

four different formats. The FORM<1:0> bits select the

format. Each of the output formats translates to a 16-bit

result on the data bus.

Write data will always be in right justified (integer)

format.

FIGURE 18-4:

A/D OUTPUT DATA FORMATS

RAM Contents:

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Read to Bus:

Signed Fractional (1.15)

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

000000

Fractional (1.15)

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

000000

Signed Integer

d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Integer

d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

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