DSPIC30F2010 datasheet(76/202 Pages) MICROCHIP

76 / 202 page

dsPIC30F2010

DS70118J-page 76

13.1

Quadrature Encoder Interface

Logic

A typical incremental (a.k.a. optical) encoder has three

outputs: Phase A, Phase B, and an index pulse. These

signals are useful and often required in position and

speed control of ACIM and SR motors.

The two channels, Phase A (QEA) and Phase B (QEB),

have a unique relationship. If Phase A leads Phase B,

then the direction (of the motor) is deemed positive or

forward. If Phase A lags Phase B, then the direction (of

the motor) is deemed negative or reverse.

A third channel, termed index pulse, occurs once per

revolution and is used as a reference to establish an

absolute position. The index pulse coincides with

Phase A and Phase B, both low.

13.2

16-bit Up/Down Position Counter

Mode

The 16-bit Up/Down Counter counts up or down on

every count pulse, which is generated by the difference

of the Phase A and Phase B input signals. The counter

acts as an integrator, whose count value is proportional

to position. The direction of the count is determined by

the

UPDN

signal,

which

generated

the

Quadrature Encoder Interface Logic.

13.2.1

POSITION COUNTER ERROR

CHECKING

Position count error checking in the QEI is provided for

and indicated by the CNTERR bit (QEICON<15>). The

error checking only applies when the position counter

is configured for Reset on the Index Pulse modes

(QEIM<2:0> = ‘110’ or ‘100’). In these modes, the

contents of the POSCNT register is compared with the

values (0xFFFF or MAXCNT + 1, depending on direc-

tion). If these values are detected, an error condition is

generated by setting the CNTERR bit and a QEI count

error interrupt is generated. The QEI count error

interrupt can be disabled by setting the CEID bit

(DFLTCON<8>). The position counter continues to

count encoder edges after an error has been detected.

The POSCNT register continues to count up/down until

a natural rollover/underflow. No interrupt is generated

for the natural rollover/underflow event. The CNTERR

bit is a read/write bit and reset in software by the user.

13.2.2

POSITION COUNTER RESET

The Position Counter Reset Enable bit, POSRES

(QEI<2>) controls whether the position counter is reset

when the index pulse is detected. This bit is only

applicable when QEIM<2:0> = ‘100’ or ‘110’.

If the POSRES bit is set to ‘1’, then the position counter

is reset when the index pulse is detected. If the

POSRES bit is set to ‘0’, then the position counter is not

reset when the index pulse is detected. The position

counter will continue counting up or down, and will be

reset on the rollover or underflow condition.

When selecting the INDX signal to reset the position

counter (POSCNT), the user has to specify the states

on QEA and QEB input pins. These states have to be

matched in order for a reset to occur. These states are

selected by the IMV<1:0> bit in the DFLTCON <10:9>

The IMV<1:0> (Index Match Value) bit allows the user

to specify the state of the QEA and QEB input pins

during an index pulse when the POSCNT register is to

be reset.

In 4X Quadrature Count Mode:

IMV1

= Required state of phase B input signal for

match on index pulse

IMV0

= Required state of phase A input signal for

match on index pulse

In 2X Quadrature Count Mode:

IMV1

= Selects phase input signal for index state

match (0 = Phase A, 1 = Phase B)

IMV0

= Required state of the selected phase input

signal for match on index pulse

The interrupt is still generated on the detection of the

index pulse and not on the position counter overflow/

underflow.

13.2.3

COUNT DIRECTION STATUS

As mentioned in the previous section, the QEI logic

generates an UPDN signal, based upon the relation-

ship between Phase A and Phase B. In addition to

the output pin, the state of this internal UPDN signal

is supplied to a SFR bit UPDN (QEICON<11>) as a

read-only bit.

Note:

QEI pins are multiplexed with analog

inputs. User must insure that all QEI asso-

ciated pins are set as digital inputs in the

ADPCFG register.

DSPIC30F2010 датащи(PDF) 76 Page - Microchip Technology

DSPIC30F2010 датащи(HTML) 76 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL