DSPIC30F2010 datasheet(32/202 Pages) MICROCHIP

32 / 202 page

dsPIC30F2010

DS70118J-page 32

4.1.2

MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a working register (i.e., the

Addressing mode can only be register direct), which is

referred to as Wb. Operand 2 can be a W register,

fetched from data memory, or 5-bit literal. The result

location can be either a W register or an address

location.

The

following

Addressing

modes

are

supported by MCU instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• 5-bit or 10-bit Literal

4.1.3

MOVE AND ACCUMULATOR

INSTRUCTIONS

Move instructions and the DSP Accumulator class of

instructions provide a greater degree of addressing

flexibility than other instructions. In addition to the

Addressing modes supported by most MCU instruc-

tions, Move and Accumulator instructions also support

mode, also referred to as Register Indexed mode.

In summary, the following Addressing modes are

supported by Move and Accumulator instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

4.1.4

MAC

INSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSAC

and MSC), also

referred to as MAC instructions, utilize a simplified set of

Addressing modes to allow the user to effectively

manipulate the data pointers through register indirect

tables.

The two source operand prefetch registers must be a

member of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 will always be directed to the X

RAGU and W10 and W11 will always be directed to the

Y AGU. The effective addresses generated (before and

after modification) must, therefore, be valid addresses

within X data space for W8 and W9 and Y data space

for W10 and W11.

In summary, the following Addressing modes are

supported by the MAC class of instructions:

• Register Indirect

• Register Indirect Post-modified by 2

• Register Indirect Post-modified by 4

• Register Indirect Post-modified by 6

• Register Indirect with Register Offset (Indexed)

4.1.5

OTHER INSTRUCTIONS

Besides the various Addressing modes outlined above,

some instructions use literal constants of various sizes.

For example, BRA (branch) instructions use 16-bit

signed literals to specify the branch destination directly,

whereas the DISI instruction uses a 14-bit unsigned

literal field. In some instructions, such as ADD Acc, the

source of an operand or result is implied by the opcode

itself. Certain operations, such as NOP, do not have any

operands.

Note:

Not

all

instructions

support

all

the

Addressing modes given above. Individ-

ual instructions may support different

subsets of these Addressing modes.

Note:

For the MOV instructions, the Addressing

mode specified in the instruction can differ

for the source and destination EA. How-

ever, the 4-bit Wb (Register Offset) field is

shared

between

both

source

and

destination (but typically only used by

one).

Note:

Not

all

instructions

support

all

the

Addressing modes given above. Individ-

ual instructions may support different

subsets of these Addressing modes.

Note:

Addressing is only available for W9 (in X

space) and W11 (in Y space).

DSPIC30F2010 датащи(PDF) 32 Page - Microchip Technology

DSPIC30F2010 датащи(HTML) 32 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL