DSPIC30F2010 datasheet(112/202 Pages) MICROCHIP

112 / 202 page

dsPIC30F2010

DS70118J-page 112

18.1

A/D Result Buffer

The module contains a 16-word dual port read-only buf-

fer, called ADCBUF0 through ADCBUFF, to buffer the

ADC results. The RAM is 10 bits wide, but is read into dif-

ferent format 16-bit words. The contents of the sixteen

ADC conversion result buffer registers, ADCBUF0

through ADCBUFF, cannot be written by user software.

18.2

Conversion Operation

After the ADC module has been configured, the sample

acquisition is started by setting the SAMP bit. Various

sources, such as a programmable bit, timer time-outs

and external events, will terminate acquisition and start

a conversion. When the A/D conversion is complete,

the result is loaded into ADCBUF0...ADCBUFF, and

the A/D interrupt flag ADIF and the DONE bit are set

after the number of samples specified by the SMPI bit.

The following steps should be followed for doing an

A/D conversion:

Configure the ADC module:

- Configure analog pins, voltage reference

and digital I/O

- Select A/D input channels

- Select A/D conversion clock

- Select A/D conversion trigger

- Turn on A/D module

Configure A/D interrupt (if required):

- Clear ADIF bit

- Select A/D interrupt priority

Start sampling.

Wait the required acquisition time.

Trigger acquisition end, start conversion

Wait for A/D conversion to complete, by either:

- Waiting for the A/D interrupt

- Waiting for the DONE bit to get set

Read A/D result buffer, clear ADIF if required.

18.3

Selecting the Conversion

Sequence

Several groups of control bits select the sequence in

which the A/D connects inputs to the sample/hold

channels, converts channels, writes the buffer memory,

and generates interrupts. The sequence is controlled

by the sampling clocks.

The

SIMSAM

bit

controls

the

acquire/convert

sequence for multiple channels. If the SIMSAM bit is

‘0’, the two or four selected channels are acquired and

converted sequentially, with two or four sample clocks.

If the SIMSAM bit is ‘1’, two or four selected channels

are acquired simultaneously, with one sample clock.

The channels are then converted sequentially. Obvi-

ously, if there is only one channel selected, the

SIMSAM bit is not applicable.

The CHPS bits selects how many channels are sam-

pled. This can vary from 1, 2 or 4 channels. If CHPS

selects 1 channel, the CH0 channel will be sampled at

the sample clock and converted. The result is stored in

the buffer. If CHPS selects 2 channels, the CH0 and

CH1 channels will be sampled and converted. If CHPS

selects 4 channels, the CH0, CH1, CH2 and CH3

channels will be sampled and converted.

The SMPI bits select the number of acquisition/conver-

sion sequences that would be performed before an

interrupt occurs. This can vary from 1 sample per

interrupt to 16 samples per interrupt.

The user cannot program a combination of CHPS and

SMPI bits that specifies more than 16 conversions per

interrupt, or 8 conversions per interrupt, depending on

the BUFM bit. The BUFM bit, when set, will split the

16-word results buffer (ADCBUF0...ADCBUFF) into

two 8-word groups. Writing to the 8-word buffers will be

alternated on each interrupt event. Use of the BUFM bit

will depend on how much time is available for moving

data out of the buffers after the interrupt, as determined

by the application.

If the processor can quickly unload a full buffer within

the time it takes to acquire and convert one channel,

the BUFM bit can be ‘0’ and up to 16 conversions may

be done per interrupt. The processor will have one

sample and conversion time to move the sixteen

conversions.

If the processor cannot unload the buffer within the

acquisition and conversion time, the BUFM bit should

be ‘1’. For example, if SMPI<3:0> (ADCON2<5:2>) =

0111

, then eight conversions will be loaded into 1/2

of the buffer, following which an interrupt occurs. The

next eight conversions will be loaded into the other

1/2 of the buffer. The processor will have the entire

time

between

interrupts

move

the

eight

conversions.

The ALTS bit can be used to alternate the inputs

selected during the sampling sequence. The input mul-

tiplexer has two sets of sample inputs: MUX A and

MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are

selected for sampling. If the ALTS bit is ‘1’ and

SMPI<3:0> = 0000, on the first sample/convert

sequence, the MUX A inputs are selected, and on the

next acquire/convert sequence, the MUX B inputs are

selected.

The CSCNA bit (ADCON2<10>) will allow the CH0

channel inputs to be alternately scanned across a

selected number of analog inputs for the MUX A group.

The inputs are selected by the ADCSSL register. If a

particular bit in the ADCSSL register is ‘1’, the corre-

sponding input is selected. The inputs are always

scanned from lower to higher numbered inputs, starting

after each interrupt. If the number of inputs selected is

greater than the number of samples taken per interrupt,

the higher numbered inputs are unused.

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