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ADSP-21469KBZ-ENG2 датащи(PDF) 15 Page - Analog Devices

номер детали ADSP-21469KBZ-ENG2
подробное описание детали  SHARC Processor material that is subject to change without notice
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ADSP-21469KBZ-ENG2 датащи(HTML) 15 Page - Analog Devices

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ADSP-21469/ADSP-21469W
Preliminary Technical Data
Rev. PrB
|
Page 15 of 56
|
November 2008
DATA MODES
The address and data pins of the external memory interface are
muxed (using bits in the SYSCTL register) to support the exter-
nal memory interface data (input/output), the PDAP (input
only), and the FLAGS (input/output). Table 7 provides the pin
settings.
BOOT MODES
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see Timing Specifications and
Figure 3 on Page 19.
Table 7. Function of Data Pins
DATA PIN MODE
AMI_ADDR [23:8]
AMI_ADDR [7:0]
AMI_DATA [7:0]
000
AMI_ADDR [23:0]
AMI_DATA [7:0]
001
Reserved
010
Reserved
011
FLAGS/PWM [15–0]
FLAGS [15–0]
100
Reserved
101
PDAP (DATA + CTRL)
FLAGS [7–0]
110
Reserved
111
Three-state all pins
Table 8. Boot Mode Selection
BOOTCFG2–0
Booting Mode
000
SPI Slave Boot
001
SPI Master Boot
010
AMI user boot (for 8-bit Flash boot)
011
Reserved
100
Link Port 0 Boot
101
Reserved
110
Reserved
111
Reserved
Table 9. Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1–0
Core to CLKIN Ratio
00
6:1
01
32:1
11
Reserved
10
16:1



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