ADSP-21469KBZ-ENG2 datasheet(14/56 Pages) AD

14 / 56 page

Rev. PrB

Page 14 of 56

November 2008

ADSP-21469/ADSP-21469W

Preliminary Technical Data

TCK

I (pu)

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be

asserted (pulsed low) after power-up or held low for proper operation of the

ADSP-21469.

TRST

I (pu)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted

(pulsed low) after power-up or held low for proper operation of the ADSP-

21469. TRST has a fixed internal pull-up resistor1, 2.

EMU

O/T (pu)

High-Z

Emulation Status. Must be connected to the ADSP-21469 Analog Devices

DSP Tools product line of JTAG emulators target board connector only. EMU

has a fixed internal pull-up resistor1, 2.

CLK_CFG1–0

Core to CLKIN Ratio Control. These pins set the start up clock frequency. See

Table 9 for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL

multiplier and divider in the PMCTL register at any time after the core comes

out of reset.

BOOT_CFG2–0

Boot Configuration Select. These pins select the boot mode for the proces-

sor. The BOOTCFG pins must be valid before reset is asserted. See Table 8 for

a description of the boot modes.

RESET

I (pu)

Processor Reset. Resets the ADSP-21469 to a known state. Upon deassertion,

there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core

begins program execution from the hardware reset vector address. The RESET

input must be asserted (low) at power-up.

XTAL

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an

external crystal.

CLKIN

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21469 clock

input. It configures the ADSP-21469 to use either its internal clock generator

or an external clock source. Connecting the necessary components to CLKIN

and XTAL enables the internal clock generator. Connecting the external clock

to CLKIN while leaving XTAL unconnected configures the ADSP-21469 to use

the external clock source such as an external clock oscillator. CLKIN may not

be halted, changed, or operated below the specified frequency.

CLKOUT/

RESETOUT/

RUNRSTIN

I/O (pu)

Clock Out/Reset Out/Running Reset In. The functionality can be switched

between the PLL output clock and reset out by setting Bit 12 of the PMCTL

The functionality of which is enabled by setting bit 0 of the RUNRSTCTL

Reference.

BR6-1

I/O

High-Z/

Driven low

Bus request. Bus request pins for external DDR2 bus arbitration.

RPBA

Rotating priority bus arbitration.

ID2-0

Chip ID

1 Pull-up/pull-down resistor can not be enabled/disabled and the value of the pull-up/pull-down resistor cannot be programmed.

2 Range of fixed pull-up resistor can be between 26k-63k

Ω. Range of fixed pull-down resistor can be between 31k-85kΩ.

Table 6. Pin List (Continued)

Name

Type

LVTTL SSTL18

State

During

and After

Reset

Description

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