ADSP-21469KBZ-ENG2 datasheet(35/56 Pages) AD

35 / 56 page

ADSP-21469/ADSP-21469W

Preliminary Technical Data

Rev. PrB

Page 35 of 56

November 2008

Table 32. Serial Ports—Enable and Three-State

Parameter

Min

Max

Unit

Switching Characteristics

tDDTEN

Data Enable from External Transmit SCLK

TBD

tDDTTE

Data Disable from External Transmit SCLK

TBD

tDDTIN

Data Enable from Internal Transmit SCLK

TBD

1 Referenced to drive edge.

Table 33. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

tDDTLFSE

Data Delay from Late External Transmit FS or External Receive FS

with MCE = 1, MFD = 0

TBD

tDDTENFS

Data Enable for MCE = 1, MFD = 0

TBD

1 The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

Figure 22. External Late Frame Sync1

1 This figure reflects changes made to support left-justified sample pair mode.

DRIVE

SAMPLE

DRIVE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DRIVE

SAMPLE

DRIVE

LATE EXTERNAL TRANSMIT FS

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

1STBIT

2ND BIT

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

1STBIT

2ND BIT

tHFSE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1PINS.

THE CHARACTERIZED AC SPORT TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES

ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH SAU.

tHFSE/I

ADSP-21469KBZ-ENG2 датащи(PDF) 35 Page - Analog Devices

ADSP-21469KBZ-ENG2 датащи(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

датащи скачать

ссылки URL