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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADSP-21469KBZ-ENG2 датащи(PDF) 44 Page - Analog Devices |
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ADSP-21469KBZ-ENG2 датащи(HTML) 44 Page - Analog Devices |
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44 / 56 page  Rev. PrB | Page 44 of 56 | November 2008 ADSP-21469/ADSP-21469W Preliminary Technical Data S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the TBD × FS clock. Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing Parameter Min Max Unit Switching Characteristics tDFSI LRCLK Delay After SCLK TBD TBD ns tHOFSI LRCLK Hold After SCLK TBD TBD ns tDDTI Transmit Data Delay After SCLK TBD TBD ns tHDTI Transmit Data Hold After SCLK TBD TBD ns tSCLKIW 1 Transmit SCLK Width TBD TBD ns 1 SCLK frequency is TBD x FS where FS = the frequency of LRCLK. Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing DRIVE EDGE SAMPLE EDGE DAI_P20-1 (SCLK) DAI_P20-1 (FS) DAI_P20-1 (DATA CHANNEL A/B) tSCLKIW tDFSI tDDTI tHOFSI tHDTI |
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