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ADSP-21469KBZ-ENG2 датащи(PDF) 31 Page - Analog Devices

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ADSP-21469KBZ-ENG2 датащи(HTML) 31 Page - Analog Devices

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ADSP-21469/ADSP-21469W
Preliminary Technical Data
Rev. PrB
|
Page 31 of 56
|
November 2008
Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 27. Memory Write—Bus Master
Parameter
Min
Max
Unit
Timing Requirements
tDAAK
AMI_ACK Delay from Address, Selects1, 2
TBD
TBD
ns
tDSAK
AMI_ACK Delay from AMI_WR Low 1, 3
TBD
TBD
ns
Switching Characteristics
TBD
TBD
tDAWH
Address, Selects to AMI_WR Deasserted2
TBD
TBD
ns
tDAWL
Address, Selects to AMI_WR Low2
TBD
TBD
ns
tWW
AMI_WR Pulse Width
TBD
TBD
ns
tDDWH
Data Setup Before AMI_WR High
TBD
TBD
ns
tDWHA
Address Hold After AMI_WR Deasserted
TBD
TBD
ns
tDWHD
Data Hold After AMI_WR Deasserted
TBD
TBD
ns
tDATRWH
Data Disable After AMI_WR Deasserted4
TBD
TBD
ns
tWWR
AMI_WR High to AMI_WR, AMI_RD Low
TBD
TBD
ns
tDDWR
Data Disable Before AMI_RD Low
TBD
TBD
ns
tWDE
AMI_WR Low to Data Enabled
TBD
TBD
ns
W = (number of wait states specified in AMICTLx register) × tSDDR2_CLKH = (number of hold cycles specified in AMICTLx register) x tDDR2_CLK
1 AMI_ACK delay/setup: System must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet tDAAK or tDSAK.
2 The falling edge of AMI_MSx is referenced.
3 Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only applies to asynchronous access mode.
4 See Test Conditions on Page 50 for calculation of hold times given capacitive and dc loads.
Figure 19. Memory Write—Bus Master
AMI_ACK
AMI_DATA
tDAWL
tWW
tDAAK
tWWR
tWDE
tDDWR
tDWHA
tDAWH
tDSAK
tDDWH
tDWHD
AMI_ADDR
MSx
AMI_WR
AMI_RD
tDATRWH



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