ADSP-21469KBZ-ENG2 datasheet(42/56 Pages) AD

42 / 56 page

Rev. PrB

Page 42 of 56

November 2008

ADSP-21469/ADSP-21469W

Preliminary Technical Data

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left justified, I2S, or right justified with word widths of 16-, 18-,

20-, or 24-bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 29 shows the right-justified mode. LRCLK is high for the

left channel and low for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data will be

right-justified to the next LRCLK transition.

Figure 30 shows the default I2S-justified mode. LRCLK is low

for the left channel and HI for the right channel. Data is valid on

the rising edge of SCLK. The MSB is left-justified to an LRCLK

transition but with a single SCLK period delay.

Figure 31 shows the left-justified mode. LRCLK is high for the

left channel and LO for the right channel. Data is valid on the

rising edge of SCLK. The MSB is left-justified to an LRCLK

transition with no MSB delay.

Figure 29. Right-Justified Mode

DAI_P20-1

LRCLK

DAI_P20-1

SCLK

DAI_P20-1

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MS B-1

MSB-2

LSB+2 L SB+1

LSBMSBMSB-1

MSB-2

LS B+2

LSB+1

LSB

MSB

Figure 30. I2S-Justified Mode

MSB-1

MS B-2

LS B+2

LSB+1

L SB

LEFT CHANNEL

RIGHT CHANNEL

MSBMS B-1

MS B-2

LSB+2

LS B+1

LSB

MSB

DAI_P20-1

LRCLK

DAI_P20-1

SCLK

DAI_P20-1

SDATA

Figure 31. Left-Justified Mode

LEFT CHANNEL

RIGHT CHANNEL

MSB-1

MSB-2

LS B+2

L SB+1

LSB

MSBMSB-1

MSB-2

LSB+2

LSB+1

L SB

MSBMSB+1

MSB

DAI_P20-1

LRCLK

DAI_P20-1

SCLK

DAI_P20-1

SDATA

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