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ADSP-21469KBZ-ENG2 датащи(PDF) 48 Page - Analog Devices

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ADSP-21469KBZ-ENG2 датащи(HTML) 48 Page - Analog Devices

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Rev. PrB
|
Page 48 of 56
|
November 2008
ADSP-21469/ADSP-21469W
Preliminary Technical Data
TWI Controller Timing
Table 45 and Figure 37 provide timing information for the TWI
interface. Input Signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DPI_P14–1 pins.
Table 45. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices1
Parameter
Standard Mode
Fast Mode
Min
Max
Min
Max
Unit
fSCL
SCL Clock Frequency
TBD
TBD
TBD
TBD
kHz
tHDSTA
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated.
TBD
TBD
μs
tLOW
Low Period of the SCL Clock
TBD
μs
tHIGH
High Period of the SCL Clock
TBD
TBD
μs
tSUSTA
Setup Time for a Repeated Start Condition
TBD
TBD
μs
tHDDAT
Data Hold Time for TWI-bus Devices
TBD
TBD
μs
tSUDAT
Data Setup Time
TBD
TBD
ns
tSUSTO
Setup Time for Stop Condition
TBD
TBD
μs
tBUF
Bus Free Time Between a Stop and Start Condition
TBD
TBD
μs
tSP
Pulse Width of Spikes Suppressed By the Input Filter n/a
n/a
TBD
TBD
ns
1 All values referred to VIHmin and VILmax levels. For more information, see Electrical Characteristics on page 17.
Figure 37. Fast and Standard Mode Timing on the TWI Bus
DPI_P14-1
SDA
DPI_P14-1
SCL
t
LOW
tHIGH
t
HDS TA
tHDDAT
t
SUDA T
t SUSTO
S
t
SU S TA
Sr
t SP
t
HD S TA
P
S
tBUF



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