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ADSP-21469KBZ-ENG2 датащи(PDF) 40 Page - Analog Devices

номер детали ADSP-21469KBZ-ENG2
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ADSP-21469KBZ-ENG2 датащи(HTML) 40 Page - Analog Devices

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Rev. PrB
|
Page 40 of 56
|
November 2008
ADSP-21469/ADSP-21469W
Preliminary Technical Data
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 37. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the PDAP, see the
PDAP chapter of the ADSP-2146x SHARC Processor Hardware
Reference. Note that the most significant 16 bits of external
PDAP data can be provided through the DATA7-0 pins. The
remaining four bits can only be sourced through DAI_P4–1.
The timing below is valid at the DATA7–0 pins.
Table 37. Parallel Data Acquisition Port (PDAP)
Parameter
Min
Max
Unit
Timing Requirements
tSPCLKEN
1
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
TBD
TBD
ns
tHPCLKEN
1
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
TBD
TBD
ns
tPDSD
1
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
TBD
TBD
ns
tPDHD
1
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
TBD
TBD
ns
tPDCLKW
Clock Width
TBD
TBD
ns
tPDCLK
Clock Period
TBD
TBD
ns
Switching Characteristics
TBD
TBD
tPDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
TBD
TBD
ns
tPDSTRB
PDAP Strobe Pulse Width
TBD
TBD
ns
1 Source pins of AMI_DATA are DATA7–0 or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
Figure 27. PDAP Timing
DAI_P20
-1
(PDAP_CLK)
SAMPLE EDGE
tPDSD
tPDHD
tSPCLKEN
tHPCLKEN
tPDCLKW
DATA
DAI_P20
-1
(PDAP_CLKEN)
tPDSTRB
tPDHLDD
DAI_P20
-1
(PDAP_STROBE)
tPDCLK



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