13892 datasheet(105/161 Pages) FREESCALE

105 / 161 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

105

13892

FUNCTIONAL DEVICE OPERATION

ADC SUBSYSTEM

Figure 28. ADC Register Set for ADC BIS Access

There are two interrupts available to inform the processor when the ADC has finished its conversions, one for the standard

ADC conversion ADCDONEI, and one for the ADCBIS conversion ADCBISDONEI. These interrupts will go high after the

conversion, and can be masked.

When two requests are queued, the request for which the trigger event occurs the first will be converted the first. During the

conversion of the first request, an ADTRIG trigger event of the other request is ignored, if for the other request the TRIGMASK

bit was set to 1. When this bit is set to 0, the other request ADTRIG trigger event is memorized, and the conversion will take place

directly after the conversions of the first request are finished.

The following diagram shows the influence of the TRIGMASK bit. The TRIGMASK bit is particularly of use when an ADC

conversion has to be lined up to a periodically ADTRIG initiated conversion. In case of ASC initiated conversions, the TRIGMASK

bit is of no influence.

Figure 29. TRIGMASK Functional Diagram

To avoid results of previous conversions getting overwritten by a periodical ADTRIG signal, a single shot function is enabled

by setting the ADONESHOT bit to a one. In that case, only at the first following conversion, an ADTRIG trigger event is accepted.

ASC events are not affected by this setting. Before performing a new single shot conversion, the ADONESHOT bit first needs to

be cleared. Note that this bit is available for each of the conversion requests 'ADC' or 'ADC BIS', so can be set independently.

It is possible to queue two ADTRIG triggered conversions. Both conversions will be executed with a priority based on the

TRIGMASK setting. If both conversion requests have identical TRIGMASK settings, priority is given to the 'ADC' conversion over

the 'ADC BIS' conversion. Note that the ADONESHOT is also taken into account.

To avoid that the ADTRIG input inadvertently triggers a conversion, the ADTRIGIGN bit can be set which will ignore any

transition on the ADTRIG pin. The ADC completely ignores either ADTRIG or ASC pulses while ADEN is low. When reading

conversion results, it is preferable to make ADEN = 0.

R/W

Bit

Address

Bits

Null

Bit

ADC

BIS0

8 Bit Address Header

24 Bit Data

ADC Control

R/W

Bit

Address

Bits

Null

Bit

ADC

BIS1

ADC Control

R/W

Bit

Address

Bits

Null

Bit

ADC

BIS2

ADC Control

R/W

Bit

Address

Bits

Null

Bit

ADC Result

Bits

ADC Result

R/W

Bit

Address

Bits

Null

Bit

ADC BIS Result

Bits

ADC Result

ADC Control

Bits

ADC Control

Bits

ADC Control

Bits

Location

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