13892 datasheet(37/161 Pages) FREESCALE

37 / 161 page

Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

CONTROL LOGIC

LICELL

Coin cell supply input and charger output. The LICELL pin provides a connection for a coin cell backup battery or supercap.

If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell

maintained logic will switch over to the LICELL for backup power. This pin also works as a current-limited voltage source for

battery charging. A small capacitor should be placed from LICELL to ground under all circumstances.

XTAL1

32.768 kHz Oscillator crystal connection 1.

XTAL2

32.768 kHz Oscillator crystal connection 2.

GNDRTC

Ground for the RTC block.

CLK32K

32 kHz Clock output for peripherals. At system start-up, the 32 kHz clock is driven to CLK32K (provided as a peripheral clock

reference), which is referenced to SPIVCC. The CLK32K is restricted to state machine activation in normal on mode.

CLK32KMCU

32 kHz Clock output for processor. At system start-up, the 32 kHz clock is driven to CLK32KMCU (intended as the CKIL input

to the system processor) referenced to VSRTC. The driver is enabled by the start-up sequencer and the CLK32KMCU is

programmable for Low Power Off mode control by the state machine.

RESETB AND RESETBMCU

Reset output for peripherals and processor respectively. These depend on the Power Control Modes of operation (See

Functional Device Operation on page 41). These are meant as reset for the processor, or peripherals in a power up condition, or

to keep one in reset while the other is up and running.

WDI

Watchdog input. This pin must be high to stay in the On mode. The WDI IO supply voltage is referenced to SPIVCC (normally

connected to SW4 = 1.8 V). SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the

system will transition to the Off state or Cold Start (depending on the configuration).

STANDBY AND STANDBYSEC

Standby input signal from processor and from peripherals respectively.

To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both

the application processor (which typically controls the STANDBY pin) and peripherals (which typically control the STANDBYSEC

pin) allow it. This is referred to as a Standby event.

The Standby pins are programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into

account the programmed input polarities associated with each pin. Since the Standby pin activity is driven asynchronously to the

system, a finite time is required for the internal logic to qualify and respond to the pin level changes.

The state of the Standby pins only have influence in the On mode and are therefore ignored during start up and in the

Watchdog phase. This allows the system to power up without concern of the required Standby polarities, since software can

make adjustments accordingly, as soon as it is running.

INT

Interrupt to processor. Unmasked interrupt events are signaled to the processor by driving the INT pin high.

13892 датащи(PDF) 37 Page - Freescale Semiconductor, Inc

13892 датащи(HTML) 37 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL