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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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13892 датащи(PDF) 48 Page - Freescale Semiconductor, Inc |
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13892 датащи(HTML) 48 Page - Freescale Semiconductor, Inc |
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48 / 161 page  Analog Integrated Circuit Device Data 48 Freescale Semiconductor 13892 FUNCTIONAL DEVICE OPERATION I2C INTERFACE Additional sense bits are available to reflect the state of the power up mode selection pins, as summarized in Table 13. LOBATHI LOBATHM LOBATHS Low battery warning Sense is 1 if above LOBATH threshold. Dual 30 μs page 55 VBUSVALIDI VBUSVALIDM VBUSVALIDS Detects A-Session Valid on VBUS Dual L2H: 20- 24 ms H2L: 8- 12 ms page 110 IDFLOATI IDFLOATM IDFLOATS ID floating detect. Sense is 1 if above threshold Dual 90 μs page 110 IDGNDI IDGNDM IDGNDS USB ID ground detect. Sense is 1 if not to ground Dual 90 μs page 110 IDFACTORYI IDFACTORYM IDFACTORYS ID voltage for Factory mode detect Sense is 1 if above threshold Dual 90 μs page 110 CHRGSE1BI CHRGSE1BM CHRSE1BS Wall charger detect Regulator short-circuit protection tripped Dual L2H 1.0 ms 200 μs page 88 SCPI SCPS - Short circuit protection trip detection L2H 0 page 71 BATTDETBI BATTDETBM BATTDETBS Battery removal detect Dual 30 ms page 99 1HZI 1HZM - 1.0 Hz time tick L2H 0 page 50 TODAI TODAM - Time of day alarm L2H 0 page 50 PWRON1I PWRON1M PWRON1S PWRON1 event Sense is 1 if pin is high. H2L 30 ms (1) page 55 L2H 30 ms page 55 PWRON2I PWRON2M PWRON2S PWRON2 event Sense is 1 if pin is high. H2L 30 ms (35) page 55 L2H 30 ms page 55 PWRON3I PWRON3M PWRON3S PWRON3 event Sense is 1 if pin is high. H2L 30 ms (35) page 55 L2H 30 ms page 55 SYSRSTI SYSRSTM - System reset through PWRONx pins L2H 0 page 55 WDIRESETI WDIRESETM - WDI silent system restart L2H 0 page 55 PCI PCM - Power cut event L2H 0 page 55 WARMI WARMM Warm Start event L2H 0 page 55 MEMHLDI MEMHLDM Memory Hold event L2H 0 page 55 CLKI CLKM CLKS Clock source change Sense is 1 if source is XTAL Dual 0 page 50 RTCRSTI RTCRSTM - RTC reset or intrusion has occurred L2H 0 page 50 THWARNHI THWARNHM THWARNHS Thermal warning higher threshold Sense is 1 if above threshold Dual 30 ms page 71 THWARNLI THWARNLM THWARNLS Thermal warning lower threshold Sense is 1 if above threshold Dual 30 ms page 71 LPBI LPBM LPBS Low power boot interrupt Dual 1.0 ms page 88 Notes 35. Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Power Control System for details. Table 12. Interrupt, Mask and Sense Bits Interrupt Mask Sense Purpose Trigger DebounceTi me Section |
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