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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DEVICE OPERATION

OPERATING MODES

TIMING DIAGRAMS

A Turn On event timing diagram example shows in Figure 12.

Figure 12. Power Up Timing Diagram

POWER UP

At power up, switchers and regulators are sequentially enabled in time slots of 2.0 ms steps to limit the inrush current after an

initial delay of 8.0 ms, in which the core circuitry gets enabled. To ensure a proper power up sequence, the outputs of the

switchers are discharged at the beginning of a Cold Start. For that reason, an 8.0 ms delay allows the outputs of the linear

regulators to be fully discharged as well through the built-in discharge path. Time slots which include multiple regulator startups

will be sub-sequenced for additional inrush balancing. The peak inrush current per event is limited. Any under-voltage detection

at BP is masked while the power up sequencer is running.

The Power Up mode Select pins (PUMS1 and 2) are used to configure the startup characteristics of the regulators. Supply

enabling and output level options are selected by hardwiring the PUMSx pins for the desired configuration. The state of the

PUMSx pins can be read out via the sense bits PUMSSxx[1:0]. Tying the PUMSx pins to ground corresponds to 00, open to 01,

VCOREDIG to 10, and VCORE to 11.

The recommended power up strategy for end products is to bring up as little of the system as possible at booting, essentially

sequestering just the bare essentials, to allow processor startup and software to run. With such a strategy, the startup transients

are controlled at lower levels, and the rest of the system power tree can be brought up by software. This allows optimization of

supply ordering where specific sequences may be required, as well as supply default values. Software code can load up all of

the required programmable options to avoid sneak paths, under/over-voltage issues, startup surges, etc., without any change in

hardware. For this reason, the Power Gate drivers are limited to activation by software rather than the sequencer, allowing the

core(s) to startup before any peripheral loading is introduced.

The power up defaults Table 26 shows the initial setup for the voltage level of the switchers and regulators, and whether they

get enabled.

Table 25. Timer Main Characteristics

Timer

Duration

Under-voltage Timer

4.0 ms

Reset Timer

40 ms

Watchdog Timer

128 ms

Power Cut Timer

Programmable 0 to 8 seconds in 31.25 ms steps

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