13892 datasheet(38/161 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

PWRON1, 2 AND 3

A turn on event can be accomplished by connecting an open drain NMOS driver to the PWRONx pin of the 13892, so that it

is in effect a parallel path for the power key.

In addition to the turn on event, the 13892A/B versions include a global reset feature on the PWRON3 pin. The 13892A version

has the global reset feature enabled by default. The 13892B version has the global reset feature disabled by default, but can be

enabled by setting the SPI bit GLBRSTENB = 0. The global reset feature powers down the part, disables the charger, resets the

SPI registers to their default value and then powers back on. To enable a global reset the PWRON3 pin needs to be pulled low

for greater than 12 seconds and then pulled back high. If the PWRON3 pin is held low for less than 12 seconds the pin will act

as a normal PWRON pin.

PUMS1 AND PUMS2

Power up mode supply setting. Default start-up of the device is selectable by hardwiring the Power Up Mode Select pins. The

Power Up Mode Select pins (PUMS1 and PUMS2) are used to configure the start-up characteristics of the regulators. Supply

enabling and output level options are selected by hardworking the PUMS pins for the desired configuration.

MODE

USB LBP mode, normal mode, test mode selection & anti-fuse bias. During evaluation and testing, the IC can be configured

for normal operation or test mode via the MODE pin as summarized in the following table.

GNDCTRL

Ground for control logic.

SPIVCC

Supply for SPI bus and audio bus

CS held low at Cold Start configures the interface for SPI mode. Once activated, CS functions as the SPI Chip Select. CS tied

to VCORE at Cold Start configures the interface for I2C mode; the pin is not used in I2C mode other than for configuration.

Because the SPI interface pins can be reconfigured for reuse as an I2C interface, a configuration protocol mandates that the

CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin).

CLK

Primary SPI clock input. In I2C mode, this pin is the SCL signal (I2C bus clock).

MOSI

Primary SPI write input. In I2C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible

addresses (A0 address selection).

MISO

Primary SPI read output. In I2C mode, this pin is the SDA signal (bi-directional serial data line).

GNDSPI

Ground for SPI interface.

MODE PIN STATE

MODE

Ground

Normal Operation

VCOREDIG

USB Low Power Boot Allowed

VCORE

Test Mode

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