13892 datasheet(99/161 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DEVICE OPERATION

ADC SUBSYSTEM

CONVERTER CORE

The ADC core is a 10 bit converter. The ADC core and logic run on 2/3 of the switcher PLL generated frequency, so

approximately 2.0 MHz. If an ADC conversion is requested while the PLL was not active, it will automatically be enabled by the

ADC. A 32.768 kHz equivalent time base is derived from this to the ADC time events. The ADC is supplied from VCORE. The

ADC core has an integrated auto calibration circuit which reduces the offset and gain errors.

The switcher PLL is programmable, see Supplies. When the switcher frequency is changed, the frequency applied to the ADC

converter will change accordingly. Although the conversion time is inversely proportional to the PLLX[2:0] setting, this will not

influence the ADC performance. The locally derived 32.768 kHz will remain constant in order not to influence the different timings

depending on this time base.

INPUT SELECTOR

The ADC has 8 input channels. Table 81 gives an overview of the attributes of the A to D channels.

The above table is valid when setting the bit ADSEL = 0 (default). If setting the bit to a 1, the touch screen interface related

inputs are mapped on the ADC channels 4 to 7 and channels 0 to 3 become unused. For more details see the touch screen

interface section.

Some of the internal signals are first scaled to adapt the signal range to the input range of the ADC. The charge current and

the battery current are indirectly read out by the voltage drop over the resistor in the charge path and battery path respectively.

For details on scaling see the dedicated readings section.

In case the source impedance is not sufficiently low on the directly accessible inputs ADIN5, ADIN6, ADIN7, and the muxed

GPO4 path, an on chip buffer can be activated through the BUFFEN bit. If this bit is set, the buffer will be active on these specific

inputs during an active conversion. Outside of the conversions the buffer is automatically disabled. The buffer will add some

offset, but will not impact INL and DNL numbers except for input voltages close to zero.

Table 81. ADC Inputs

Channel

ADA1[2:0]

ADA2[2:0]

Signal read

Input Level

Scaling

Scaled Version

000

Battery Voltage (BATT)

0 – 4.8 V

0 – 2.4 V

001

Battery Current

(BATT-BATTISNSCC)

-60 mV – 60 mV (70)

x20

-1.2 – 1.2 V

010

Application Supply (BPSNS)

0 – 4.8 V

0 – 2.4 V

011

Charger Voltage (CHRGRAW)

0 – 12 V

0 – 20 V

/10

0 – 2.4 V

100

Charger Current

(CHRGISNS-BPSNS)

-300 mV – 300 mV (71)

-1.2 – 1.2 V

101

General Purpose ADIN5

(Battery Pack Thermistor)

0 – 2.4 V

110

General Purpose ADIN6

Backup Voltage (LICELL)

0 – 2.4 V

0 – 3.6 V

x2/3

0 – 2.4 V

111

General Purpose ADIN7/ADIN7B

0 – 2.4 V

General Purpose ADIN7

0 – BP

0 – 2.4 V

General Purpose ADIN7B

0 – VIOHI

0 – 1.4 V

Die Temperature

–

1.2 – 2.4 V

UID

0 – 4.8 V

0 – 2.4 V

Notes

70.

Equivalent to -3.0 to +3.0 A of current with a 20 mOhm sense resistor

71.

Equivalent to -3.0 to +3.0 A of current with a 100 mOhm sense resistor

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