CDCE706 datasheet(33/40 Pages) TI

33 / 40 page

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fVCO − VCO Frequency − MHz Set Point

G011

TA = 25°C

VCC = 3.3 V

M div = 4

N div = 15

P div = 3

fVCO − Frequency Range

for Normal-Speed Mode

fVCO − Frequency Range

for High-Speed Mode

High-Speed Mode > 180 MHz

Normal-Speed Mode < 200 MHz

CDCE706

www.ti.com ........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008

Figure 28. Snapshot of Phase Jitter

Jitter depends on the VCO frequency (fVCO) of the PLL. A higher fVCO results in better jitter performance

compared to a lower fVCO. The VCO frequency can be defined via the M- and N-dividers of the PLL.

As the CDCE706 supports a wide frequency range, the device offers VCO frequency-selection bits, bits [7:5] of

byte 6. These bits define the jitter-optimized frequency range of each PLL. The user can select between the

normal-speed mode (80 MHz to 200 MHz) and the high-speed mode (180 MHz to 300 MHz). Figure 29 shows

the jitter performance over fVCO for the two frequency ranges.

Figure 29. Period Jitter vs fVCO for Normal-Speed Mode and High-Speed Mode

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