Cross-Coupling, Spur Suppression, and Noise Rejection

Carrier

48MHz

2

Harmonic

nd

Spurat

27MHz

· Measured Y1:48MHz

·

W

·

W

·

W

·

Y0is27MHz(XTAL Buffered,Loadedby50

)

Y2is56.448MHz(Loadedby50

)

Y3is33.33MHz(Loadedby50

)

Y4, Y5intheHigh-ImpedanceState

C003

·

·

·

Measured Y0:48MHz

Y1, Y2, Y3 Y4and Y5intheHigh-ImpedanceState

Inserted30mV,1MHzatV

=3.3V

CC

Carrier

48MHz

Carrier

48MHz

Spursat

47MHzand49MHz

Spur47MHzand

Fundamentalat1MHz

C004

Phase Noise Characteristic

CDCE706

The TI Pro Clock software automatically calculates the PLL parameter for jitter-optimized performance.

Cross-coupling in ICs occurs through interactions between several parts of the chip such as between output

stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive, and resistive (ohmic),

induced by output switching, leakage current, ground bouncing, power supply transients, etc.

The CDCE706 is designed using RFSiGe process technology. This process gives excellent performance in

linearity, low power consumption, best-in-class noise performance, and very good isolation characteristics

between the on-chip components.

The good isolation is a major benefit of the RFSiGe process because it minimizes the coupling effect. Even if all

three PLLs are active and all outputs are on, the noise suppression is well above 50 dB. Figure 30 and Figure 31

show an example of noise coupling, spur-suppression, and power-supply noise rejection of the CDCE706. The

measurement conditions are shown in Figure 30 and Figure 31.

Figure 30. Noise Coupling and Spur Suppression

Figure 31. Power-Supply Noise Rejection

In high-speed communication systems, the phase-noise characteristic of the PLL frequency synthesizer is of high

interest. Phase noise describes the stability of the clock signal in the frequency domain, similar to the jitter

specification in the time domain.

34

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