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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CDCE706 датащи(PDF) 17 Page - Texas Instruments |
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CDCE706 датащи(HTML) 17 Page - Texas Instruments |
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17 / 40 page  Functional Description of the Logic CDCE706 www.ti.com ........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 All bytes are readable/writeable, unless otherwise expressly mentioned. Byte 0 (Read-Only): Vendor Identification Bits [3:0]; Revision Code Bit [7:4](1) Revision Code Vendor Identification X X X X 0 0 0 1 (1) Byte 0 is only readable by the byte-read instruction (see Figure 8). Bytes 1 to 9: Reference Divider M of PLL1, PLL2, PLL3(1) M8 M7 M6 M5 M4 M3 M2 M1 M0 Div by Default(2) (3) 0 0 0 0 0 0 0 0 0 Not allowed 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 1 1 3 • • • 1 1 1 1 1 1 1 0 1 509 1 1 1 1 1 1 1 1 0 510 1 1 1 1 1 1 1 1 1 511 (1) By selecting the PLL divider factors, M ≤ N and 80 MHz ≤ fVCO ≤ 300 MHz. (2) Unless customer-specific setting (3) Default setting of divider M for PLL1 = 1, for PLL2 = 27, and for PLL3 = 375. Bytes 1 to 9: Feedback Divider N of PLL1, PLL2, PLL3(1) N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 Div by Default(2) (3) 0 0 0 0 0 0 0 0 0 0 0 0 Not allowed 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 1 1 3 • • • 1 1 1 1 1 1 1 1 1 1 0 1 4093 1 1 1 1 1 1 1 1 1 1 1 0 4094 1 1 1 1 1 1 1 1 1 1 1 1 4095 (1) By selecting the PLL divider factors, M ≤ N and 80 MHz ≤ fVCO ≤ 300 MHz. (2) Unless customer-specific setting (3) Default setting of divider N for PLL1 = 8, for PLL2 = 250, and for PLL3 = 3136. Byte 3 Bits [7:5]: PLL (VCO) Bypass Multiplexer PLLxMUX PLL (VCO) MUX Output Default(1) 0 PLLx Yes 1 VCO bypass (1) Unless customer-specific setting Byte 6 Bits [7:5]: VCO Frequency Selection Mode for Each PLL(1) PLLxFVCO VCO Frequency Range Default(2) 0 80 MHz–200 MHz 1 180 MHz–300 MHz Yes (1) This bit selects the normal-speed mode or the high-speed mode for the dedicated VCO in PLL1, PLL2, or PLL3. At power up, the high-speed mode is selected, fVCO is 180 MHz–300 MHz. In case of a higher fVCO, this bit must be set to 1. (2) Unless customer-specific setting Copyright © 2005–2008, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link(s): CDCE706 |
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