RECOMMENDED CRYSTAL SPECIFICATIONS

EEPROM SPECIFICATION

TIMING REQUIREMENTS

DEVICE CHARACTERISTICS

CDCE706

MIN

NOM

MAX

UNIT

Crystal input frequency range (fundamental mode)

8

27

54

MHz

ESR

15

60

Ω

Input capacitance CLK_IN0 and CLK_IN1

3

pF

(1)

For crystal frequencies above 50 MHz, the effective series resistor should not exceed 50

Ω to assure stable start-up condition.

(2)

For maximum power handling (drive level), see Figure 15.

MIN

TYP

MAX

UNIT

EEcyc

Programming cycles of EEPROM

100

1000

Cycles

EEret

Data retention

10

Years

over recommended ranges of supply voltage, load, and operating-free air temperature

MIN

NOM

MAX

UNIT

CLK_IN REQUIREMENTS

PLL mode

1

200

CLK_IN clock input frequency (LVCMOS or differential)

MHz

PLL bypass mode

0

200

Rise and fall time, CLK_IN signal (20% to 80%)

4

ns

40%

60%

SMBus TIMING REQUIREMENTS (see Figure 11)

SCLK frequency

100

kHz

START hold time

4

µs

SCLK low-pulse duration

4.7

µs

SCLK high-pulse duration

4

50

µs

START setup time

0.6

µs

SDATA hold time

0.3

µs

SDATA setup time

0.25

µs

SCLK/SDATA input rise time

1000

ns

SCLK/SDATA input fall time

300

ns

STOP setup time

4

µs

Bus free time

4.7

µs

Time in which the device must be operational after power-on reset

500

ms

over recommended operating free-air temperature range and test load (unless otherwise noted), see Figure 1

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

OVERALL PARAMETER

All PLLs on, all outputs on,

90

115

mA

Every circuit powered down except SMBus,

Power-down current

50

µA

2.1

V

control circuit

(1)

(2)

For calculating total supply current, add the current from Figure 2, Figure 3, and Figure 4. Using the high-speed mode of the VCO

reduces the current consumption. See Figure 3.

6

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