DESCRIPTION (CONTINUED)

CDCE706

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PLL2 also supports center- and down-spread-spectrum clocking (SSC). This is a common technique to reduce

electromagnetic interference. Also, the slew-rate controllable (SRC) output edges minimize EMI noise.

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically

adjusted to achieve the high stability and optimized jitter transfer characteristic of the PLL.

The device supports nonvolatile EEPROM programming for easily customized application. The device is

preprogrammed with a factory default configuration (see Figure 13) and can be reprogrammed to a different

application configuration before it goes onto the PCB or reprogrammed by in-system programming. A different

device setting is programmed via the serial SMBus interface.

Two free programmable inputs, S0 and S1, can be used to control for each application the most demanding logic

control settings (outputs disable to low, outputs 3-state, power down, PLL bypass, etc).

supplies can be 2.3 V to 3.6 V. At output voltages lower than 3.3 V, the output drive current is limited.

The CDCE706 is characterized for operation from –40°C to 85°C.

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Product Folder Link(s): CDCE706