5x6-Switch A

InputCLK

(PLL Bypass)

PLL1

PLL3

6x6-SwitchB

7-BitDivider

Y0

Y1

Y2

Y3

Y4

Y5

P0

(1...127)

P1

(1...127)

P2

(1...127)

P3

(1...127)

P4

(1...127)

P5

(1...127)

Programming

PLL2

Non-SSC

PLL2

w/SSC

B0335-02

InternalClockSources

OutputSwitchMatrix

Outputs

PLL/Input_Clk

Selection

P-Divider

Setting

P-Divider

Selection

OutputSelection:

Active/Low/3-State

Inverting/Non-Inverting

SlewRate/V

CCOUT

LVCMOS Output Configuration

CDCE706

Switch B was added to the output switch matrix to ensure that output frequencies derived from one P-divider are

100% phase-aligned. Also, the P-divider is built in a way that every divide factor is automatically duty-cycle

corrected. Changing the divider value on the fly may cause a glitch on the output.

Figure 23. CDCE706 Output Switch Matrix

In addition, the outputs can be switched active, low, high-impedance state, and/or 180-degree phase-shifted.

Also, the output slew rate and the output voltage are user-selectable.

The output stage of the CDCE706 supports all common output settings, such as enable, disable, low-state, and

signal inversion (180-degree phase shift). It further features slew-rate control (0.6 ns to 3.3 ns) and variable

output supply voltage (2.3 V to 3.6 V).

Copyright © 2005–2008, Texas Instruments Incorporated

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Product Folder Link(s): CDCE706