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CDCE706 датащи(PDF) 19 Page - Texas Instruments |
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CDCE706 датащи(HTML) 19 Page - Texas Instruments |
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19 / 40 page ![]() CDCE706 www.ti.com ........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 Byte 11, Bits [7:6]: Input Signal Source(1) IS1 IS0 Function Default(2) 0 0 CLK_IN0 is the crystal oscillator input, and CLK_IN1 serves as the crystal oscillator output. Yes CLK_IN0 and CLK_IN1 are two LVCMOS inputs. CLK_IN0 or CLK_IN1 is selectable via the CLK_SEL 0 1 control pin. 1 0 CLK_IN0 and CLK_IN1 serve as differential signal inputs. 1 1 Reserved (1) In case the crystal input or differential clock input is selected, the input clock selection, byte 10, bit [4], is not relevant. (2) Unless customer-specific setting Byte 12, Bit [6]: Power-Down Mode (Except SMBus) PD Power-Down Mode Default(1) 0 Normal device operation Yes 1 Power down(2) (1) Unless customer-specific setting (2) In power down, all PLLs and the clock-input stage go into power-down mode, all outputs are in the high-impedance state, all actual register settings are maintained, and the SMBus stays active. The power-down mode overwrites the high-impedance state or low state of the S0 and S1 settings in byte 10. Bytes 13 to 18, Bit [6:0]: Outputs Switch Matrix 6 × 7-Bit Divider P0–P5 DIVYx6 DIVYx5 DIVYx4 DIVYx3 DIVYx2 DIVYx1 DIVYx0 Div by Default(1)(2) 0 0 0 0 0 0 0 Not allowed 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 2 • • • 1 1 1 1 1 0 1 125 1 1 1 1 1 1 0 126 1 1 1 1 1 1 1 127 (1) Unless customer-specific setting (2) Default settings of divider P0 = 10, P1 = 20, P2 = 8, P3 = 9, P4 = 32, and P5 = 4. Bytes 19 to 24, Bits [5:4]: LVCMOS Output Rise/Fall Time Setting at Y0–Y5 SRCYx1 SRCYx0 Yx Default(1) 0 0 Nominal +3 ns (tr0/tf0) 0 1 Nominal +2 ns (tr1/tf1) 1 0 Nominal +1 ns (tr2/tf2) 1 1 Nominal (tr3/tf3) Yes (1) Unless customer-specific setting Bytes 19 to 24, Bits [2:0]: Outputs Switch Matrix (6 × 6 Switch B) Divider (P0–P5) Selection for Outputs Y0–Y5 SWBYx2 SWBYx1 SWBYx0 Any Output Yx Default(1) 0 0 0 Divider P0 0 0 1 Divider P1 0 1 0 Divider P2 Y0, Y1, Y2, Y3, Y4, Y5 0 1 1 Divider P3 1 0 0 Divider P4 1 0 1 Divider P5 1 1 0 Reserved 1 1 1 Reserved (1) Unless customer-specific setting Copyright © 2005–2008, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link(s): CDCE706 |
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