CDCE706 datasheet(25/40 Pages) TI

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Spread-Spectrum Clocking and EMI Reduction

CDCE706

www.ti.com ........................................................................................................................................... SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008

Divider M and divider N operate internally as a fractional divider for fVCO up to 250 MHz. This allows a fractional

divider ratio for zero-ppm output clock error.

In the case of fVCO > 250 MHz, it is recommended that only integer factors of N/M are used.

For optimized jitter performance, keep divider M as small as possible. Also, the fractional divider concept

requires a PLL divider configuration, M

≤ N (or N/M ≥ 1).

Additionally, each PLL supports two bypass options:

• PLL bypass

• VCO bypass

In PLL bypass mode, the PLL is completely bypassed, so that the input clock is switched directly to output

switch A (SWAPxx of bytes 9 to 12). In the VCO bypass mode, only the VCO of the PLL is bypassed by setting

PLLxMUX to 1 (bits [7:5] of byte 3). But divider M still is useable and expands the output divider by an additional

9 bits. This gives a total divider range of M × P = 511 × 127 = 64,897. In VCO bypass mode, the PLL block is

powered down and minimizes current consumption.

Table 3. Example for Divide, Multiplication, and Bypass Operation

fIN

fOUT-desired

fOUT-actual

Divider

Function

Equation(1)

fVCO [MHz]

[MHz]

N/M

Fractional(2)

fOUT = fIN × (N/M)/P

30.72

155.52

5.0625

155.52

Integer factor(3)

fOUT = fIN × (N/M)/P

270

VCO bypass

fOUT = fIN/(M × P)

30.72

0.06

—

(1)

P-divider of output-switch matrix is included in the calculation.

(2)

Fractional operation for fVCO ≤ 250 MHz

(3)

Integer operation for fVCO > 250 MHz

In addition to the basic PLL function, PLL2 supports spread-spectrum clocking (SSC). Thus, PLL 2 features two

outputs, an SSC output and a non-SSC output. Both outputs can be used in parallel. The mean phase of the

center-spread, SSC-modulated signal is equal to the phase of the nonmodulated input frequency. SSC is

selected by output switch A (SWAPxx of bytes 9 to 12).

SSC also is bypassable (byte 25, bits [6:4]) by powering down the SSC output and setting it to the logic-low

state. The non-SSC output of PLL2 is not affected by this mode and can still be used.

SSC is an effective method to reduce electromagnetic interference (EMI) noise in high-speed applications. It

reduces the RF energy peak of the clock signal by modulating the frequency and spreads the energy of the

signal to a broader frequency range. Because the energy of the clock signal remains constant, a varying

frequency that broadens the overtones necessarily lowers their amplitudes. Figure 19 shows the effect of SSC on

a 54-MHz clock signal for DSP.

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