CDCE706

Bytes 9 to 12: Output Switch Matrix (5 × 6 Switch A) PLL Selection for P-Divider P0–P5

SWAPx2

SWAPx1

SWAPx0

Any Output Px

0

0

0

PLL bypass (input clock)

0

0

1

PLL1

P2, P3, P4, P5

0

1

0

PLL2 non-SSC

P0

0

1

1

1

0

0

PLL3

P1

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Reserved

(1)

Unless customer-specific setting

(2)

PLL2 has an SSC output and a non-SSC output. If SSC bypass is selected (see byte 25, bits [6:4]), the SSC circuitry of PLL2 is

powered down and the SSC output is reset to logic low. The non-SSC output of PLL2 is not affected by this mode and can still be used.

Byte 10, Bits [1:0]: Configuration Settings of Input S0/A0/CLK_SEL

S01

S00

Function

If S0 is low, the PLLs and the clock-input stage go into power-down mode, outputs are in the

Yes

0

0

high-impedance state, all actual register settings are maintained, SMBus stays active. If S0 is high,

If S0 is low, the PLL and all dividers (M-Div and P-Div) are bypassed and PLL is in power down,

all outputs are active (inv. or non-inv.), actual register settings are maintained, SMBus stays

0

1

active; this mode is useful for production test. If S0 is high, then the device is powered on and

outputs are active.

1

0

—CLK_SEL when set low selects CLK_IN_IN0.

—CLK_SEL when set high selects CLK_IN_IN1.

In this mode, the control input S0 is interpreted as address bit A0 of the slave receiver address

1

1

(1)

Unless customer-specific setting

(2)

Power-down mode overwrites the high-impedance state or low state of the S1 setting in byte 10, bits [3:2].

(3)

If the clock input (CLK_IN0/CLK_IN1) is selected as crystal input or differential clock input (byte 11, bits [7:6]), then this setting is not

relevant.

(4)

To use this pin as slave receiver address bit A0, an initialization pattern must be sent to the CDCE706. When S00/S01 is set to 1, the

S0 input pin is interpreted in the next read or write cycle as address bit A0 of the slave receiver address byte. Note that right after

byte 10 (S00/S01) has been written, A0 (via the S0-pin) is immediately active (also when byte 10 is sent within a block-write sequence).

After the initialization, each CDCE706 has its own S0-dependent slave receiver address and can be addressed according to its new

valid address.

Byte 10, Bits [3:2]: Configuration Settings of Input S1/A1

S11

S10

Function

If S1 is set low, all outputs are switched to a low-state (non-inv.) or high-state (inv.). If S1 is high, then all

Yes

0

0

the outputs are active.

If S1 is set low, all outputs are switched to a high-impedance state. If S1 is high, then all the outputs are

0

1

active.

1

0

Reserved

1

1

(1)

Unless customer-specific setting

(2)

To use this pin as slave-receiver address bit A1, an initialization pattern must be sent to the CDCE706. When S10/S11 is set to be 1,

the S1 input pin is interpreted in the next read or write cycle as address bit A1 of the slave receiver address byte. Note that right after

byte 10 (S10/S11) has been written, A1 (via the S1-pin) is immediately active (also when byte 10 is sent within a block-write sequence).

After the initialization, each CDCE706 has its own S1-dependent slave receiver address and can be addressed according to its new

valid address.

CLKSEL

Input Clock

0

CLK_IN0

Yes

1

CLK_IN1

(1)

This bit is not relevant if crystal input or differential clock input is selected, byte 11, bits [7:6].

(2)

Unless customer-specific setting

18

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