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DM9102DEP датащи(PDF) 33 Page - Davicom Semiconductor, Inc. |
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DM9102DEP датащи(HTML) 33 Page - Davicom Semiconductor, Inc. |
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33 / 70 page ![]() Final 33 Version: DM9102D-DS-F01 May 10, 2006 6.3.1 Basic Mode Control Register (BMCR) – 0 Bit Name Default Description 15 Reset 0, RW/SC Reset: 1=Software reset 0=Normal operation This bit resets the status and controls the PHY registers of the DM9102D to their default states. This bit, which is self-clearing, will keep its value until the reset process is completed 14 Loopback 0, RW Loopback: 1=Loop-back enabled 0=Normal operation When in 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data to the MAC. 13 Speed Selection 1, RW Speed Select: 1=100Mbps 0=10Mbps Link speed may be selected either by this bit or by Auto-negotiation. When Auto-negotiation is enabled and bit 12 is set, this bit will reflect Auto- negotiation selected media type. 12 Auto-negotiation Enable 1, RW Auto-negotiation Enable: 1= Auto-negotiation enabled: bit 8 and 13 will report Auto-negotiation status 0= Auto-negotiation disabled: bit 8 and 13 will determine the link speed and duplex mode 11 Power Down 0, RW Power Down: Setting this bit will power down the internal PHY except crystal / oscillator circuit. 1=Power Down 0=Normal Operation 10 Reserved 0,RO Reserved. Write as 0, ignore on read. 9 Restart Auto-negotiation 0,RW/SC Restart Auto-negotiation: 1= Restart Auto-negotiation. Re-initiates the Auto-negotiation process. When Auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep its value until Auto-negotiation is initiated by the DM9102D. The operation of the Auto-negotiation process will not be affected by the management entity that clears this bit. 0= Normal Operation 8 Duplex Mode 1,RW Duplex Mode: 1= Full Duplex operation. Duplex selection is allowed when Auto-negotiation is disabled (bit 12 of this register is cleared). With Auto-negotiation enabled, this bit reflects the duplex capability selected by Auto-negotiation. 0= Normal operation 7 Collision Test 0,RW Collision Test: 1= Collision Test enabled. When set in half duplex mode, the DM9102D will enter collision state if packet transmission is in progress. 0= Normal Operation 6:0 Reserved <0000000>, RO Reserved. Write as 0, ignore on read 6.3.2 Basic Mode Status Register (BMSR) – 1 |
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