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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM9102DEP датащи(PDF) 15 Page - Davicom Semiconductor, Inc. |
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DM9102DEP датащи(HTML) 15 Page - Davicom Semiconductor, Inc. |
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15 / 70 page  Final 15 Version: DM9102D-DS-F01 May 10, 2006 6.1.4 Miscellaneous Function (xxxxxx0cH - PCILT) 31 16 15 0 87 23 24 BIST Header Type Latency Timer Cache Line Size Built-In Self Test Header Type Latency Timer For The Bus Master Cache Line Size For Memory Read Bit Default Type Description 31:24 00H RO Built In Self Test ( 00H means No Implementation) 23:16 00H RO Header Type ( 00H means single function with Predefined Header Type ) If pin 75 IDSEL2 is pull-high, header type is 80H means multiple function is present. 15:8 00H RW Latency Timer For The Bus Master The latency timer is guaranteed by the system and measured by clock cycles. When the FRAME# is asserted at the beginning of a master period by the DM9102D, the value will be copied into a counter and start counting down. If the FRAME# is de-asserted prior to count expiration, this value is meaningless. When the count expires before GNT# is de-asserted, the master transaction will be terminated as soon as the GNT# is removed While GNT# signal is removed and the counter is non-zero, the DM9102D will continue with its data transfers until the count expires. The system host will read MIN_GNT and MAX_LAT registers to determine the latency requirement for the device and then initialize the latency timer with an appropriate value The reset value of Latency Timer is determined by BIOS 7:0 00H RO Cache Line Size For Memory Read Mode Selection ( 00H means No Implementation For Use) 6.1.5 I/O Base Address (xxxxxx10H - PCIIO) 31 0 1 7 8 1 0000000 I/O Base Address I/O Base Address PCI I/O Range Indication I/O or Memory Space Indicator |
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