DM9102DEP datasheet(24/70 Pages) DAVICOM

24 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

Move data from host memory to transmit FIFO

Close descriptor by clearing owner bit of descriptor

Waiting end of transmit

Transmit end and Close descriptor by writing status

Transmit process suspend

19:17

RXPS

000,RO

Receive Process State

These bits are read only and used to indicate the state of receive process. The

mapping table is shown below

Bit19 Bit18 Bit17

Process State

Receive process stopped

Fetch receive descriptor

Wait for receive packet under buffer available

Move data from receive FIFO to host memory

Close descriptor by clearing owner bit of descriptor

Close descriptor by writing status

Receive process suspended due to buffer unavailable

Purge the current frame from received FIFO

because of the unavailable received buffer

NIS

0,RW

Normal Interrupt Summary

Normal interrupt includes any of the three conditions:

CR5<0> – TXCI: Transmit Complete Interrupt

CR5<2> – TXDU: Transmit Buffer Unavailable

CR5<6> – RXCI: Receive Complete Interrupt

AIS

0,RW

Abnormal Interrupt Summary

Abnormal interrupt includes any interrupt condition as shown below, excluding

Normal Interrupt conditions. They are TXPS (bit1), TXJT (bit3), TXFU (bit5), RXDU

(bit7), RXPS (bit8), RXWT (bit9), SBE (bit13).

Reserved

0,RO

Reserved

SBE

0,RW

System Bus Error

The PCI system bus errors will set this bit. The type of system bus error is shown in

CR5<25:23>.

LINK

0,RW

Link Change Status

This bit is set to indicate that the link status changed in internal PHYceiver.

11:10

Reserved

0,RO

Reserved

RXWT

0,RW

Receive Watchdog Timer Expired

This bit is set to indicate that the receive watchdog timer has expired

RXPS

0,RW

Receive Process Stopped

This bit is set to indicate that the receive process enters the stopped state.

RXDU

0,RW

Receive Buffer Unavailable

This bit is set when the DM9102D fetches the next receive descriptor that is still

owned by the host. Receive process will be suspended until a new frame enters or

the receive polling command is set.

RXCI

0,RW

Receive Complete Interrupt

This bit is set when a received frame is fully moved into host memory and receive

status has been written to descriptor. Receive process is still running and continues to

fetch next descriptor.

TXFU

0,RW

Transmit FIFO Underrun

This bit is set when transmit FIFO has underrun condition during the packet

transmission. It may happen due to the heavy load on bus, cause transmit buffer

unavailable before end of packet. In this case, transmit process is placed in the

suspend state and underrun error TDES0<1> is set.

Reserved

0,RO

Reserved

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