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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM9102DEP датащи(PDF) 18 Page - Davicom Semiconductor, Inc. |
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DM9102DEP датащи(HTML) 18 Page - Davicom Semiconductor, Inc. |
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18 / 70 page  18 Final Version: DM9102D-DS-F01 May 10, 2006 6.1.10 Interrupt & Latency Configuration (xxxxxx3cH - PCIINT) 31 16 15 0 87 23 24 MAX_LAT MIN_GNT INT_PIN INT_LINE Maximum Latency Timer Minimum Grant Interrupt Pin Interrupt Line Bit Default Type Description 31:24 28H RO Maximum Latency Timer that can be sustained. 23:16 14H RO Minimum Grant Minimum Length of a Burst Period. 15:8 01H RO Interrupt Pin read as 01H to indicate INTA# 7:0 XXH RW Interrupt Line that Is routed to the Interrupt Controller The value depends on system software. 6.1.11 Device Specific Configuration Register (xxxxxx40H- PCIUSR) 31 30 29 16 15 8 0 Reserved 27 26 28 7 25 24 23 Device Specific Link Event enable/disable Sample Frame Event enable/disable Magic Packet Event enable/disable Link Event Status Sample Frame Event Status Magic Packet Event Status Device Specific Reserved Bit Default Type Description 31 0 RW Device Specific Bit (sleep mode) 30 0 RW Device Specific Bit (snooze mode) 29 0 RW When set, enables Link Status Change Wake up Event 28 0 RW When set, enables Sample Frame Wake up Event 27 0 RW When set, enables Magic Packet Wake up Event 26 0 RO When set, indicates the Link Change and the Link Status Change Event occurred 25 0 RO When set, indicates the Sample Frame is received and the Sample Frame match Event occurred 24 0 RO When set, indicates the Magic Packet is received and the Magic packet Event occurred 23:16 00H RO Reserved Bits Read As 0 15:8 00H RW Device Specific 7:0 00H RO Reserved Bits Read As 0 |
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