DM9102DEP datasheet(25/70 Pages) DAVICOM

25 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

TXJT

0,RW

Transmit Jabber Expired

This bit is set when the transmitted data is over 2048 byte

Transmit process will be aborted and placed in the stop state. It also causes transmit

jabber timeout TDES0<14> to assert.

TXDU

0,RW

Transmit Buffer Unavailable

This bit is set when the DM9102D fetches the next transmit descriptor that is still

owned by the host. Transmit process will be suspended until the transmission polling

command is set.

TXPS

0,RW

Transmit Process Stopped

This bit is set to indicate transmit process enters the stopped state.

TXCI

0,RW

Transmit Complete Interrupt

This bit is set when a frame is fully transmitted and transmit status has been written to

descriptor (the TDES1<31> is also asserted). Transmit process is still running and

continues to fetch next descriptor.

6.2.7 Network Operation Mode Register (CR6)

987

Bit

Name

Default

Description

Reserved

0,RO

Must be Zero

RXA

0,RW

Receive All

When set, all incoming packet will be received, regardless the destination address.

The address match is checked according to theCR6<7>, CR6<6>, CR6<4>,

CR6<2>, CR6<0>, and RDES0<30> will show this match

NPFIFO

0,RW

Set to not purge RX FIFO for test only if RX buffer unavailable.

28:26

Reserved

000,RO

Must be Zero

Reserved

1,RO

Must be One

24:23

Reserved

00,RO

Must be Zero

TXTM

1,RW

Transmit Threshold Mode

When set, the transmit threshold mode is 10Mb/s. When reset, the threshold mode

is 100Mb/s. This bit is used together with CR6<15:14> to decide the exact

threshold level.

SFT

0,RW

Store and Forward Transmit

When set, the packet transmission will be started after a full frame has been moved

from the host memory to transmit FIFO. When reset, the packet transmission’s start

will depend on the threshold value specified in CR6<15:14>.

Reserved

0,RW

Reserved

0,RW

Reserved

External

MII_ Mode

1,RW

In external MII mode, use this bit to enable or disable internal PHY

See page 56 “7.8 External MII Interface” for details.

Reserved

0,RO

Reserved

1PKT

0,RW

One Packet Mode

When this bit is set, only one packet is stored at TX FIFO

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