DM9102DEP datasheet(35/70 Pages) DAVICOM

35 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

The PHY Identifier Register#1 and Register#2 work together in a single identifier of the DM9102D. The Identifier consists of a

concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number.

DAVICOM Semiconductor's IEEE assigned OUI is 00606E.

Bit

Name

Default

Description

15:.0

OUI_MSB

<0181H>,

RO/P

OUI Most Significant Bits:

This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this register

respectively. The most significant two bits of the OUI are ignored (the IEEE

standard refers to these as bit 1 and 2)

6.3.4 PHY Identifier Register #2 (PHYIDR2) - 3

Bit

Name

Default

Description

15:10

OUI_LSB

<101110>,

RO/P

OUI Least Significant Bits:

Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register

respectively

9:.4

VNDR_MDL

<001010>,

RO/P

Vendor Model Number:

Six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit

3:0

MDL_REV

<0000>,

RO/P

Model Revision Number:

Four bits of vendor model revision number mapped to bit 3 to 0 (most

significant bit to bit 3)

6.3.5 Auto-negotiation Advertisement Register (ANAR) – 4

This register contains the advertised abilities of this DM9102D device as they will be transmitted to its link partner during

Auto-negotiation.

Bit

Name

Default

Description

0,RO/P

Next Page Indication:

0=No next page available

1=Next page available

The DM9102D has no next page, so this bit is permanently set to 0

ACK

0,RO

Acknowledge:

1=Link partner ability data reception acknowledged

0=Not acknowledged

The DM9102D's Auto-negotiation state machine will automatically control this

bit in the outgoing FLP bursts and set it at the appropriate time during the

Auto-negotiation process. Software should not attempt to write to this bit.

0, RW

Remote Fault:

1=Local Device senses a fault condition

0=No fault detected

12:11

Reserved

00, RW

Reserved:

Write as 0, ignore on read

FCS

0, RW

Flow Control Support:

1=Controller chip supports flow control ability.

0=Controller chip doesn’t support flow control ability.

0, RW

100BASE-T4 Support:

1=100BASE-T4 is supported by the local device.

0=100BASE-T4 is not supported.

The DM9102D does not support 100BASE-T4 so this bit is 0 permanently

TX_FDX

1, RW

100BASE-TX Full Duplex Support:

1=100BASE-TX Full Duplex is supported by the local device.

0=100BASE-TX Full Duplex is not supported.

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