DM9102DEP datasheet(14/70 Pages) DAVICOM

14 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

Setting this bit will enable the DM9102D to assert PERR# on the detection

of a data parity error and to assert SERR# for reporting address parity

error

VGA Palette Snooping (0 for No Support)

Memory Write and Invalid (0 for No Implementation)

The DM9102D only generates memory write cycle

Special Cycles (0 for No Implementation)

Master Device Capability Enable/Disable

When this bit is set, DM9102D has the ability of master mode operation

Memory Space Access Enable/Disable

This bit controls the ability of memory space access. The memory access

includes memory mapped I/O access and Boot ROM access. As the

system boots up, this bit will be enabled by BIOS for Boot ROM memory

access. While in normal operation, using memory mapped I/O access,

this bit should be set by driver before memory access cycles

I/O Space Access Enable/Disable

This bit controls the ability of I/O space access. It will be set by BIOS after

power on

6.1.3 Revision ID (xxxxxx08H - PCIRV)

Revision ID

Class Code

Revision Major Number

Revision Minor Number

Bit

Default

Type

Description

31:8

020000H

Class Code (020000H)

This is the standard code for Ethernet LAN controller

7:4

0101

Revision Major Number

This is the silicon-major revision number that will increase for the subsequent

versions of the DM9102D

3:0

0001

Revision Minor Number

This is the silicon-minor revision number that will increase for the subsequent

versions of the DM9102D

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