DM9102DEP datasheet(9/70 Pages) DAVICOM

9 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

TEST1

TEST Mode Control 1

In normal operation, tie low to this pin.

WOL

Wake up signal.

The DM9102D can assert this pin if it detects link status

change, magic packet, or sample frame match. The default is

low active pulse mode. The DM9102D also supports High/Low

and Pulse/Level options from EEPROM setting.

Crystal feedback output

This pin is used for crystal connection only. Leave this pin open

if oscillator is used.

X1/OSC

Crystal or Oscillator Input. (25MHz±50ppm)

Connect to a 25MHz Oscillator or series resonance,

fundamental frequency crystal.

102

BGRES

Bandgap Voltage Reference Resistor.

It connects to a 6.8KΩ1% error tolerance resistor between this

pin and BGRESG pin, to provide an accurate current reference

for DM9102D (10Base-T/100Base-TX Application).

116

ISOLATE#

Isolate

This pin is used to isolate the DM9102D from the PCI bus.

VCTRL25

Voltage 2.5V control

This pin can be used to control a BJT transistor ‘s base pin to

generate a stable 2.5V power in BJT’s drain pin .

5.6 Power Pins

Pin No.

128LQFP

Pin Name

I/O

Description

101

BGRESG

Bandgap Ground

It is used together with the BGRES pin.

100,107,108

AGND

Analog Ground

103,104,111,112

AVDD25

Analog Power, +2.5V

AVDD

Analog Power, +3.3V

8,9,15,22,28,29,35,45,

46,58,76,86,99,125

DGND

Digital Ground

82,120

DVDD25

Digital Power, +2.5V

4,5,12,18,19,25,32,42,52,

53,61,70

DVDD

Digital Power, +3.3V

DM9102DEP датащи(PDF) 9 Page - Davicom Semiconductor, Inc.

DM9102DEP датащи(HTML) 9 Page - Davicom Semiconductor, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

датащи скачать

ссылки URL