ATtiny25 datasheet(125/196 Pages) ATMEL

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7598H–AVR–07/09

ATtiny25/45/85

The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is

written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the nor-

mal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as

a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to

this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of the selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the data registers are updated. The ADC

Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,

ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on

ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions

are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the system clock frequency and the input clock

to the ADC.

Table 18-5.

ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

128

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