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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny25 датащи(PDF) 87 Page - ATMEL Corporation |
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ATtiny25 датащи(HTML) 87 Page - ATMEL Corporation |
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87 / 196 page  87 7598H–AVR–07/09 ATtiny25/45/85 14.1.5 Timer/Counter1 Output Compare RegisterB - OCR1B The output compare register B is an 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow- ing the compare event. 14.1.6 Timer/Counter1 Output Compare RegisterC - OCR1C The output compare register C is an 8-bit read/write register. The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C value. A software write that sets TCNT1 and OCR1C to the same value does not generate a compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1. This register has the same function in normal mode and PWM mode. 14.1.7 Timer/Counter Interrupt Mask Register - TIMSK • Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. • Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. • Bit 5 - OCIE1B: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector $009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. Bit 7 6 543210 $2D ($4D) MSB LSB OCR1B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 000000 Bit 765 43210 $2B ($4B) MSB LSB OCR1C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 111 11111 Bit 7 6 5 4 3 2 1 0 $39 ($59) - OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 - TIMSK Read/Write R R/W R/W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 0 0 |
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