ATtiny25 datasheet(45/196 Pages) ATMEL

45 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

8.10.2

Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A

timed sequence is needed when changing the Watchdog Time-out period. To change the

Watchdog Time-out, the following procedure must be followed:

In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence.

Within the next four clock cycles, in the same operation, write the WDP bits as desired,

but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

Interrupts

This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85.

For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”

on page 11.

9.1

Interrupt Vectors in ATtiny25/45/85

Table 9-1.

Reset and Interrupt Vectors

Vector

No.

Program

Address

Source

Interrupt Definition

0x0000

RESET

External Pin, Power-on Reset, Brown-out Reset,

Watchdog Reset

0x0001

INT0

External Interrupt Request 0

0x0002

PCINT0

Pin Change Interrupt Request 0

0x0003

TIM1_COMPA

Timer/Counter1 Compare Match A

0x0004

TIM1_OVF

Timer/Counter1 Overflow

0x0005

TIM0_OVF

Timer/Counter0 Overflow

0x0006

EE_RDY

EEPROM Ready

0x0007

ANA_COMP

Analog Comparator

0x0008

ADC

ADC Conversion Complete

0x0009

TIM1_COMPB

Timer/Counter1 Compare Match B

0x000A

TIM0_COMPA

Timer/Counter0 Compare Match A

0x000B

TIM0_COMPB

Timer/Counter0 Compare Match B

0x000C

WDT

Watchdog Time-out

0x000D

USI_START

USI START

0x000E

USI_OVF

USI Overflow

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