ATtiny25 datasheet(32/196 Pages) ATMEL

32 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

• Bit 2 – BODSE: BOD Sleep Enable

BOD disable functionality is available in some devices, only. See “Limitations” on page 33.

The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD

disable is controlled by a timed sequence.

This bit is unused in devices where software BOD disable has not been implemented and will

read as zero in those devices.

7.2

Idle Mode

When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the

interrupt system to continue operating. This sleep mode basically halts clk

CPU and clkFLASH, while

allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,

the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator

Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the

ADC is enabled, a conversion starts automatically when this mode is entered.

7.3

ADC Noise Reduction Mode

When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise

Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the

Watchdog to continue operating (if enabled). This sleep mode halts clk

I/O, clkCPU, and clkFLASH,

while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change

interrupt can wake up the MCU from ADC Noise Reduction mode.

7.4

Power-down Mode

When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the

Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a

Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the

MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules

only.

Table 7-1.

Sleep Mode Select

SM1

SM0

Sleep Mode

Idle

ADC Noise Reduction

Power-down

Stand-by mode

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