ATtiny25 datasheet(29/196 Pages) ATMEL

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7598H–AVR–07/09

ATtiny25/45/85

6.9

Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-

cuits on the system. Note that the clock will not be output during reset and the normal operation

of I/O pin will be overridden when the fuse is programmed. Any clock source, including the inter-

nal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock

Prescaler is used, it is the divided system clock that is output.

6.10

System Clock Prescaler

The ATtiny25/45/85 system clock can be divided by setting the Clock Prescale Register –

CLKPR. This feature can be used to decrease power consumption when the requirement for

processing power is low. This can be used with all clock source options, and it will affect the

clock frequency of the CPU and all synchronous peripherals. clk

I/O, clkADC, clkCPU, and clkFLASH

are divided by a factor as shown in Table 6-13.

6.10.1

Clock Prescale Register – CLKPR

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting

the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 6..4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-13.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

Bit

3210

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Read/Write

R/W

Initial Value

See Bit Description

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