ATtiny25 datasheet(69/196 Pages) ATMEL

69 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the

polarity of the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform

generated will have a maximum frequency of f

OC0 = fclk_I/O/2 when OCR0A is set to zero. This

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

12.6.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In

non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare

Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while

down-counting. In inverting Output Compare mode, the operation is inverted. The dual-slope

operation has lower maximum operation frequency than single slope operation. However, due to

the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor con-

trol applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 12-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x

and TCNT0.

Figure 12-7. Phase Correct PWM Mode, Timing Diagram

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

TCNTn

Period

OCn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

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