ATtiny25 datasheet(55/196 Pages) ATMEL

55 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

• Port B, Bit 4- XTAL2/CLKO/ADC2/OC1B/PCINT4

XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal

calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can not be used

as an I/O pin. When using internal calibratable RC Oscillator or External clock as a Chip clock

sources, PB4 serves as an ordinary I/O pin.

CLKO: The devided system clock can be output on the pin PB4. The divided system clock will be

output if the CKOUT Fuse is programmed, regardless of the PORTB4 and DDB4 settings. It will

also be output during reset.

ADC2: Analog to Digital Converter, Channel 2.

OC1B: Output Compare Match output: The PB4 pin can serve as an external output for the

Timer/Counter1 Compare Match B when configured as an output (DDB4 set). The OC1B pin is

also the output pin for the PWM mode timer function.

PCINT4: Pin Change Interrupt source 4.

• Port B, Bit 3 - XTAL1/ADC3/OC1B/PCINT3

XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal calibrateble

RC oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

ADC3: Analog to Digital Converter, Channel 3.

OC1B: Inverted Output Compare Match output: The PB3 pin can serve as an external output for

the Timer/Counter1 Compare Match B when configured as an output (DDB3 set). The OC1B pin

is also the inverted output pin for the PWM mode timer function.

PCINT3: Pin Change Interrupt source 3.

• Port B, Bit 2 - SCK/ADC1/T0/USCK/SCL/INT0/PCINT2

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDPB2. When the pin is

forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.

ADC1: Analog to Digital Converter, Channel 1.

T0: Timer/Counter0 counter source.

USCK: Three-wire mode Universal Serial Interface Clock.

SCL: Two-wire mode Serial Clock for USI Two-wire mode.

INT0: External Interrupt source 0.

PCINT2: Pin Change Interrupt source 2.

• Port B, Bit 1 - MISO/AIN1/OC0B/OC1A/DO/PCINT1

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a

Master, this pin is configured as an input regardless of the setting of DDB1. When the SPI is

enabled as a Slave, the data direction of this pin is controlled by DDB1. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB1 bit.

AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

ATtiny25 датащи(PDF) 55 Page - ATMEL Corporation

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