AT697F datasheet(59/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

empty bit UASx TSx. Transmission resumes and the UASx TSx is cleared when a new char-

acter is loaded in the transmitter holding register.

If the transmitter is disabled, it will continue operating until the character currently being transmit-

ted is completely sent out. The transmitter holding register cannot be loaded when the

transmitter is disabled.

If flow control is enabled, the CTS input must be low in order for the character to be transmitted.

If it is deasserted in the middle of a transmission, the character in the shift register is transmitted

and the transmitter serial output then remains inactive until CTS is asserted again. If the CTS is

connected to a receivers RTS, overrun can effectively be prevented.

Receiver Operation

The receiver is enabled for data reception when the receiver enable bit UACx REx is set logical

one. The receiver looks for a high to low transition of a start bit on the receiver serial data input

pin. If a transition is detected, the state of the serial input is sampled a half bit clocks later. If the

serial input is sampled high the start bit is invalid and the search for a valid start bit continues. If

the serial input is still low, a valid start bit is assumed and the receiver continues to sample the

serial input at one bit time intervals until the proper number of data bits and the parity bit have

been assembled and one stop bit has been detected. During this process the least significant bit

is received first.

The serial input is sampled three times for each bit and averaged to filter out noise.

The data is then transferred to the receiver holding register and the data ready bit UASx DRx is

set logical one. The parity, framing and overrun error bits are set at the received byte boundary,

at the same time as the receiver ready bit is set.

If both receiver holding and shift registers contain an un-read character when a new start bit is

detected, then the character held in the receiver shift register will be lost and the overrun bit

UASx OVx is set logical one.

If flow control is enabled, then the RTS will be negated (high) when a valid start bit is detected

and the receiver holding register contains an un-read character. When the holding register is

read, the RTS will automatically be reasserted again.

A correctly received byte is indicated by the data ready bit UASx DRx. In case of error (framing

error, stop bit error,...), the respective bits UASx FEx, UASx PEx, ... are set logical one when

the data ready bit remains logical zero.

Interrupt Generation

The two UARTs can be configured to generate interrupt each time a byte is received or a byte is

sent.

If the UACx TIx is set logical one, an interrupt is issued after each character sending. If set log-

ical zero, no interrupt is issued on character sending.

If the UACx RIx is set logical one, an interrupt is issued after each character reception. If set

logical zero, no interrupt is issued after a character reception.

If the receiver interrupt is enabled, when error is detected during the reception of a character,an

interrupt is generated. To identify the origin of the transaction failure, refer to the uart status reg-

ister bits (UASx OVx, UASx PEx, UASx TEx) that indicate either it is a parity, a framing or an

overrun error.

Loop back mode

If the UACx LBx is set, the UART will be in loop back mode. In this mode, the transmitter output

is internally connected to the receiver input and the RTS is connected to the CTS. It is then pos-

sible to perform loop back tests to verify operation of receiver, transmitter and associated

software routines. In this mode, the outputs remain in the inactive state, in order to avoid send-

ing out data.

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