AT697F datasheet(43/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

Cache

Memories

Overview

The AT697F processor implements a Harvard architecture with separate instruction and data

buses, connected to two independent cache controllers. In order to improve the speed perfor-

mance of the cpu core, multi-set-caches are used for both instruction and data caches.

The cache replacement policy used for both instruction and data caches is based on the LRU

algorithm. The least recently used (LRU) set of the cache is replaced when new data need to be

stored in cache.

Cache mapping

Most of the main memory areas can be cached. The cacheable areas are the PROM and RAM

areas. The following table presents the caching capabilities of the processor.

Table 17.

Address Range

Area

Cache status

0x00000000 - 0x1FFFFFFF

PROM

Cached

0x20000000 - 0x3FFFFFFF

I/O

Non-cacheable

0x40000000 -0x7FFFFFFF

RAM

Cached

0x80000000 -0xFFFFFFFF

Internal

Non-cacheable

Cache Capability List

Operation

During normal operation, the processor accesses instructions and data using ASI 0x8 - 0xB as

defined in the SPARC standard.

Using the LDA/STA instructions, alternative address spaces as caches can be accessed.

ASI[3:0] are used for the mapping when ASI[7:4] have no influence on operation.

•

Access with ASI 0 - 3 will force a cache miss, update the cache if the data was previously

cached or allocate a new line if the data was not in the cache and the address refers to a

cacheable location.

•

Access to ASI 4 and 7 will force a cache miss and update the cache if the data was

previously cached.

The following table shows the ASI implementation on the AT697F.

Table 18. ASI Usage

ASI

Usage

0x0, 0x1, 0x2, 0x3

Forced cache miss (replace if cacheable)

0x4, 0x7

Forced cache miss (update on hit)

0x5

Flush instruction cache

0x6

Flush data cache

0x8, 0x9, 0xA, 0xB

Normal cached access (replace if cacheable)

0xC

Instruction cache tags

0xD

Instruction cache data

0xE

Data cache tags

0xF

Data cache data

Note:

Please refer to the SPARC v8 specification for detailed information on ASI usage.

Instruction Cache

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