AT697F datasheet(58/155 Pages) ATMEL

58 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

If used, the parity bit is located between the last data bit and the stop bit of the serial frame.

The relation between the parity bit and data bits is as follows:

even

…

odd

⊕

⊕⊕⊕⊕⊕

…

⊕

⊕⊕⊕⊕⊕

even

Parity bit using even parity

odd

Parity bit using odd parity

Data bit n of the character

Clock Generation

The clock generation logic generates the base clock for the Transmitters and Receivers. The bit rate of the

UART is issued from the clock generator after a combination between the input clock of the clock module

and a scaler.

Uart Clock

Two clock inputs can be used by the clock generator :

•

An internal clock

•

An external clock

Each UART can be configured to use either the internal or the external clock source by program-

ming the UACx

ECx. If set logical zero, the UART is clocked by the internal clock. If

UACx ECx is set logical one, the UART is clocked by the external clock. When using the exter-

nal configuration, the UART clock shall be provided by PIO[3] from the general purpose

interface. This clock input is used as an alternate function for PIO[3].

caution :

When using the external clock source, the frequency of PIO[3] must be less than half the fre-

quency of the system clock.

Baud Rate Generation

To generate the bit-rate, each UART has a programmable 12-bits clock divider (UASCAx).

According to the configuration of the UACx ECx, the scaler is clocked either by the system or

by an external clock.

Each time the scaler underflows, a UART tick is generated. The scaler is automatically reloaded

with the value of the UART scaler register after each underflow. The resulting UART tick fre-

quency should be 8 times the desired baud-rate.

The following equation shall be used to calculate the scaler value to define, depending on the

clock source and the expected baud rate.

scaler

uartclk

baudrate

---------------------------------

–

-------------------------------------------

variable description :

•

uartclk : frequency of the uart clock

•

baudrate : expected baud rate

•

scaler : value to set in (UASCAx) to reach the expected baudrate

Communication

Operations

UARTS operations are controlled through the uart control registers (UACx) and the Uart status

registers (UASx).

Transmitter Operation

The transmitter is enabled setting logical one the UACx TEx . When ready to transmit, data is

transferred from the transmitter holding register to the transmitter shift register and converted to

a serial frame on the transmitter serial output pin (TX).

Following the transmission of the stop bit, if a new character is not available in the transmitter

holding register, the transmitter serial data output remains high and the transmitter shift register

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