AT697F datasheet(15/155 Pages) ATMEL

15 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

AT697F CPU

Core

This section discusses the SPARC core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories, perform cal-

culations, control peripherals, and handle interrupts.

SPARC

Architecture

Overview

The AT697F CPU core is based on the LEON2 architecture.

Figure 2. Block diagram of the AT697F Integer Unit architecture

alu/shift

mul/div

regfile

D-cache

address/dataout

datain

operand2

rs1

imm, tbr, wim, psr

wres

result

ytmp

Decode

Execute

Memory

Write

rs2

rs1

tbr, wim, psr

jmpl address

ex pc

d_pc

jmpa

f_pc

Add

call/branch address

tbr

‘0’

e_pc

m_pc

w_pc

d_inst

e_inst

m_inst

w_inst

Fetch

I-cache

address

data

The AT697F integer unit (IU) implements SPARC integer instructions as defined in SPARC

Architecture Manual version 8. The IU is designed for highly dependable space and military

applications by including fault tolerance features.

To execute instructions at a rate approaching one instruction per clock cycle, the IU employs a

five-stage instruction pipeline that permits parallel execution of multiple instructions.

•

Instruction Fetch: If the instruction cache is enabled, the instruction is fetched from the

instruction cache. Otherwise, the fetch is forwarded to the memory controller. The instruction

is valid at the end of this stage and is latched inside the IU.

•

Decode: The instruction is decoded and the operands are read. Operands may come from

the register file or from internal data bypasses. CALL and Branch target addresses are

generated in this stage.

•

Execute: ALU, logical, and shift operations are performed. For memory operations and for

JMPL/RETT, the address is generated.

•

Memory: Data cache is accessed. For cache reads, the data will be valid by the end of this

stage, at which point it is aligned as appropriate. Store data read out in the Execute stage is

written to the data cache at this time.

•

Write: The result of any ALU, logical, shift, or cache read operations re written back to the

All five stages operate in parallel, working on up to five different instructions at a time. A basic

’single-cycle’ instruction enters the pipeline and completes in five cycles.

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