AT697F datasheet(68/155 Pages) ATMEL

68 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

TAP Architecture

The TAP implemented in the AT697 consists of a TAP interface, a TAP controller, plus a number

of shift registers including an instruction register (IR) and some registers .

Figure 43. AT697 TAP Architecture

TCK

Reset

TRST

TAP

Controller

TDO

TDI

TMS

TCK

Clock DR

Shift DR

Update DR

Clock IR

Shift IR

Update IR

∇

. . . .

Select

Ena TDO

Design-Specific Data

Mux

. . . .

. . . . . . . . .

Test

Data Registers

Instruction Decode

Instruction Register

Bypass Register

Boundary Scan Register

Device ID Register

TAP Controller

The TAP controller is a synchronous finite state machine (FSM) which controls the sequence of

operations of the JTAG test circuitry, in response to changes at the JTAG bus. (Specifically, in

response to changes at the TMS input with respect to the TCK input.)

The TAP controller FSM implements the state (16 states) diagram as detailed in the following

diagram. The IR is a 3-bit register which allows a test instruction to be shifted into the AT697.

The instruction selects the test to be performed and the test data register to be accessed.

Although any number of loops may be supported by the TAP, the finite state machine in the TAP

controller only distinguishes between the IR and a DR. The specific DR can be decoded from the

instruction in the IR.

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