AT697F datasheet(87/155 Pages) ATMEL

87 / 155 page

AT697F ADVANCE INFORMATION

7703C–AERO–6/09

12..9

rambs[3:0]

SRAM bank size.

Defines the size of each ram bank

“0000” = 8 Kbyte,

“0001” = 16 Kbyte,

...

“1111” = 256 Mbyte.

rambrdy

RAM area bus ready enable.

For RAM Bank 4 (RAMSN[4]). If set to one, a RAM access will be extended until BRDY* is asserted (driven

low).

rmw

Read-modify-write.

if set, Enable read-modify-write cycles on sub-word writes to 32-bit areas with common write strobe (no byte

write strobe).

5..4

ramwdh[1:0]

SRAM bus width.

Defines the data with of the SRAMarea:

“00” = 8 bits,

“1X” = 32 bits.

3..2

ramwws[1:0]

SRAM write waitstates.

Defines the number of waitstates during SRAM write cycles:

“00” = 0 waitstate,

“01” = 1 waitstates,

“10” = 2 waitstates,

“11” = 3 waitstates.

1..0

ramrws[1:0]

SRAM read waitstates.

Defines the number of waitstates during SRAM read cycles:

“00” = 0 waitstate,

“01” = 1 waitstates,

“10” = 2 waitstates,

“11” = 3 waitstates.

Table 47. Memory Configuration Register 3 - MCFG3

Address = 0x80000008

reserved

srcrv[14:0]

tcb[6:0]

r/w

r/w r/w r/w r/w

r/w

11101

xxx xxxx xxxx xxxx

xxxx xxxx

Bit Number

Mnemonic

Description

26..12

srcrv[14:0]

SDRAM refresh counter reload value.

EDAC diagnostic write bypass

EDAC diagnostic read bypass

RAM EDAC enable.

Enable EDAC checking of the RAM area

PROM EDAC enable.

Enable EDAC checking of the PROM area. At reset, this bit is initialised with the value of PIO[2]

7..0

tcb[6:0]

Test checkbits.

This field replaces the normal checkbits during store cycles when WB is set. TCB is also loaded with the

memory checkbits during load cycles when RB is set.

Bit Number

Mnemonic

Description

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