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AT697F датащи(PDF) 104 Page - ATMEL Corporation |
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AT697F датащи(HTML) 104 Page - ATMEL Corporation |
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104 / 155 page ![]() 104 7703C–AERO–6/09 AT697F ADVANCE INFORMATION Interrupt can be forced by setting a bit in the interrupt force register. IU acknowledgement will clear the force bit. Table 79. Interrupt Clear Register - ITC Address = 0x8000009C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved iclear[14:0] r/w r r/w xxxx xxxx xxxx xxxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x Bit Number Mnemonic Description 15..1 iclear[14:0] Interrupt clear If written with a ‘1’, will clear the corresponding bit(s) in the interrupt pending register. Aread return zero. Table 80. Secondary Interrupt Mask Register - SITM Address = 0x800000B0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 simask[31:0] r/w 0000 0000 0000 0000 0000 0000 0000 0000 Bit Number Mnemonic Description 32..0 simask[31:0] Second interrupt mask indicates whether an interrupt is masked (simask[n] = ‘0’) or enabled (simask[n] = ’1’) After reset, the interrupt mask register is set to all zeros while the remaining control registers are undefined. . Table 81. Secondary Interrupt Pending Register - SITP Address = 0x800000B4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sipend[31:0] r/w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Bit Number Mnemonic Description 32..0 sipend[31:0] Second interrupt pending indicates whether a iterrupt is pending (sipend[n] = ‘1’) . Table 82. Secondary Interrupt Status Register - SITS Address = 0x800000B8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ip irl[4:0] r/w r/w r/w xxxx xxxx xxxx xxxx xxxx xxxx xx x x xxxx |
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